Design Guideline for Mode Generation
For test signal limitations :
Avoid using shared pin(s) for scan_mode and scan_enable.
Avoid using bi-directional ports as test_clock、scan_mode and scan_enable signals.
Mode Generation Module with limitations.
Using Dedicated test pins for scan_mode and scan_enable; 參考DFT (十四)
Using Internal-pins as scan_mode. 參考DFT (十五)
Treat functional output of in-out pin as scan_mode 參考DFT (十六)
2011年8月13日 星期六
2011年8月12日 星期五
DFT再了解(十二)
Architecture of Mode Generation Module
There are three main blocks included, a mode generator, an I/O control
signal generator, and a signal multiplexer.
Mode Generator
The mode generator takes the operation mode switch pin “Opmode_in” and the
mode selection pin “mode_sel” to generate a bunch of test-enable signals.
When any one of the test-enable signals is enabled. the chip is set to test mode.
I/O control signal generator
The I/O control signal generator controls the share of function pins to deliver
data-in and control signals.
These shared pins can be input pins or in-out pins.
If the in-out pins are shared and the test mode is enabled, the I/O control signal
generator issues I/O control signals to place the shared pin in the input status.
Signal multiplexer
The signal multiplexer creates the paths for DFT designs and the shared pins.
If a DFT designs is placed in the test mode, the test signals and data pins of
DFT designs are connected to the primary inputs of shared pins.
Therefore, the DFT designs can be tested via the primary inputs.
There are three main blocks included, a mode generator, an I/O control
signal generator, and a signal multiplexer.
Mode Generator
The mode generator takes the operation mode switch pin “Opmode_in” and the
mode selection pin “mode_sel” to generate a bunch of test-enable signals.
When any one of the test-enable signals is enabled. the chip is set to test mode.
I/O control signal generator
The I/O control signal generator controls the share of function pins to deliver
data-in and control signals.
These shared pins can be input pins or in-out pins.
If the in-out pins are shared and the test mode is enabled, the I/O control signal
generator issues I/O control signals to place the shared pin in the input status.
Signal multiplexer
The signal multiplexer creates the paths for DFT designs and the shared pins.
If a DFT designs is placed in the test mode, the test signals and data pins of
DFT designs are connected to the primary inputs of shared pins.
Therefore, the DFT designs can be tested via the primary inputs.
2011年8月11日 星期四
H265-High Efficiency Video Coding
新的國際影像壓縮標準
中文wiki http://zh.wikipedia.org/wiki/High_Efficiency_Video_Coding
英文wiki比較詳細
http://en.wikipedia.org/wiki/High_Efficiency_Video_Coding
中文wiki http://zh.wikipedia.org/wiki/High_Efficiency_Video_Coding
英文wiki比較詳細
http://en.wikipedia.org/wiki/High_Efficiency_Video_Coding
H.265是ITU-T VCEG 繼H.264之後所制定的新規格。
H.265最初設想作為一個完全新的標準，而不是H.264的改良與延伸。一些協定有關的各項目標的H.265項目已達成的，如計算效率，高壓縮性能[1][2]，但仍不成熟。
NGVC想要將bitrate減少了50％，同時主要圖像質量和計算複雜性與H.264相比，計算複雜度從提升到3倍。
以下較詳細內容是轉貼自 http://silentlain.pixnet.net/blog/post/26643909
HEVC 是由MPEG和VCEG聯合開發的下一代video coding standard，目前由Joint Collaborative Team on Video Coding (JCT-VC)主導，目標是希望在相同解析度下，能用一半bitrate達到現在H. 264的畫質。
雖然JCT-VC在2010年才成立，VCEG在2005就開始著手規劃下一代video coding standard，並寫了Key Technology Areas (KTA) software，各家廠商再依照KTA，各自implement一套codec來競爭，最後勝出的版本經過修改後成為reference codec，成為接下來改進的基準。
第一階段已於2010年結束，現在大家基於新的reference codec (HM)繼續整合/加入各種新的功能/演算法，預計2013年完成standard。
有別於H. 264，這次HEVC在一開始就明確訂定兩個不同的方向：High Efficiency (HE)和Low Complexity (LC)。HE主要瞄準高解析度(>1080P, etc. 4K*2K, 8K*4K)，希望能以現在H. 264一半的bitrate達到類似的畫質，因應未來更高解析度的需求；LC則把目標放在720P~1080P，希望能達到比H. 264更低的decoding complexity，主要應用在mobile平台。我想有這樣的發展一方面是因為Smart Phone/Tablet的興起，另一方面也是因為H. 264剛出來時，雖然compression ratio很驚人，但實在是太吃資源，所以這次在開發時把硬體資源列入重要考量。
相較於H. 264，目前HE已經可以在相似畫質下降低43%流量；LC的部分，目前已經可以做到H. 264 74% decoding time (both based on HM2.0 v.s. JM17)，距離目標是不遠了。
Trivia：
1. 總共有27個proposal參加第一階段競爭，其中25個來自業界(Samsung, Qualcomm, NTT, Panasonic, Nokia, Microsoft, Sony, Sharp, Huawai, Intel, MediaTek...)，2個來自學術界(NCTU, Taiwan, RWTH aachen University, Germany)，最後獲得第一名是 Samsung，所以目前reference codec是以 Samsung's proposal 為基準下去改寫，三星能夠打贏其他所有公司/學校，技術力不容小覷，未來HEVC (正式名稱應該會是H.265)標準一旦定案，Samsung 光是靠Patent就躺著賺了。目前HM裡面有個filter的名字就叫做"Samsung 12-tap interpolation filter"，看了實在很不是滋味...
2. 台灣目前有兩家在搞這塊，MTK和NCTU。做Video codec很多時間花在驗證，以現在HEVC來說，每次要提出新的功能/改進都需要encode 147段影片，然後比較數據，NCTU目前用128顆CPU encode，需要大約2週才能run完一個完整的測試，MTK據說有一個CPU Farm，裡面有4000個CPU，三天就可以run完測試，只能說業界果然是資本雄厚...
參考網址
各家提案的資料網站
http://www.birds-eye.net/definition/acronym/?id=1299441836測試Video
http://www.streetfire.net/video/test-video-h265-flvmov_part-1_640055.htm
h265-Full video download
http://www.filestube.com/h/h265
測試軟體網站 http://www.h265.net/
軟體下載區: https://hevc.hhi.fraunhofer.de/svn/svn_HEVCSoftware/tags/HM-1.0/
所有版本 : https://hevc.hhi.fraunhofer.de/svn/svn_HEVCSoftware/tags/
KTA軟體下載
http://iphome.hhi.de/suehring/tml/download/KTA/
H265標準初稿 下載
另外一個文件網站 http://wftp3.itu.int/av-arch/jctvc-site
未來藍圖
The timescale for completing the HEVC standard is The timescale for completing the HEVC standard is as follows:
1 February 2012: Committee Draft (complete draft of February 2012: Committee Draft (complete draft of standard)
2 July 2012: Draft International Standard July 2012: Draft International Standard
3 January 2013: Final Draft International Standard (ready January 2013: Final Draft International Standard (ready to be ratified as a Standard)
DFT再了解(十一)
Reserved Signals for Whole Chip Scan Implementation
The standard cell portion of the chip design except macro blocks is implemented
with an internal scan.
The interfaces for the internal scan implementation should be reserved advance.
The signals reserved include scan_clock, test_reset, scan_enable, scan_in,
scan_out, and scan_mode (｀1＇ in scan & ATPG mode).
The signals scan_enable, scan_in_0, and scan_in_n are connected between Mode
Generation Module and Core. They are left floating and wait for DFT implementation.
The scan output signals scan_out_0, and scan_out_n are tied to 0 in the boundary of
Debug Module and wait for DFT implementation.
The standard cell portion of the chip design except macro blocks is implemented
with an internal scan.
The interfaces for the internal scan implementation should be reserved advance.
The signals reserved include scan_clock, test_reset, scan_enable, scan_in,
scan_out, and scan_mode (｀1＇ in scan & ATPG mode).
The signals scan_enable, scan_in_0, and scan_in_n are connected between Mode
Generation Module and Core. They are left floating and wait for DFT implementation.
The scan output signals scan_out_0, and scan_out_n are tied to 0 in the boundary of
Debug Module and wait for DFT implementation.
2011年8月10日 星期三
Design Compiler再了解(四十四)
Output Data的用法
# Insert buffers for all multiple-port nets – eliminate assign
set_fix_multiple_port_nets –all –buffer_constants
compile ... or compile_ultra ...
# Convert tri to wire - eliminate assign
set verilogout_no_tri true
# Eliminate special characters in the netlist and constraints file
change_names –rules verilog –hierarchy
write –f ddc –hierarchy –output my_ddc.ddc
write –f verilog –hierarchy –output my_verilog.v
# Write out the constraints-only sdc file
write_sdc my_design.sdc
# Write out the scan chain information
write_scan_def –out my_design.def
# Write out the physical constraints
write_physical_constraints –output PhysConstr.tcl
Note: set_fix_multiple_port_netsmust be applied before compiling the design, because
the fix happens during compile – it is recommended to do so before the first compile.
The set verilogout_no_tri trueand change_namescommands should be applied after
all optimizations, just prior to writing out the netlist and/or constraints.
# Insert buffers for all multiple-port nets – eliminate assign
set_fix_multiple_port_nets –all –buffer_constants
compile ... or compile_ultra ...
# Convert tri to wire - eliminate assign
set verilogout_no_tri true
# Eliminate special characters in the netlist and constraints file
change_names –rules verilog –hierarchy
write –f ddc –hierarchy –output my_ddc.ddc
write –f verilog –hierarchy –output my_verilog.v
# Write out the constraints-only sdc file
write_sdc my_design.sdc
# Write out the scan chain information
write_scan_def –out my_design.def
# Write out the physical constraints
write_physical_constraints –output PhysConstr.tcl
Note: set_fix_multiple_port_netsmust be applied before compiling the design, because
the fix happens during compile – it is recommended to do so before the first compile.
The set verilogout_no_tri trueand change_namescommands should be applied after
all optimizations, just prior to writing out the netlist and/or constraints.
DFT再了解(十)
DFT Integration Architecture
The DFT integration architecture should follow the suggestions below:
To accommodate the different test requirements, mode generator and multiple test architecture must be provided on the same test design.
In order to observe the boundary signals of a specific building block in normal
mode or test output signals in different test modes , the plan must be provided to
enable debugging function flexibility
When the I/O pin count is a limited design resource, the test pins used in DFT implementation should be shared with the chip function pins.
The shared pins will be applied to DFT control signals or data input/output signals.
The shared pins could be input、output or bi-directional pins
If the shared pins as bi-directional pins should be controlled to place in the input
status or output status.
The test clock and test reset signals should be easily controllable.
There are four main blocks added in the integration architecture, Mode Generation
Module, Debug Module, Clock Manage Module and Reset Manage Module.
Mode Generation Module and Debug Module:
The function of Mode Generation Module is mainly used to generate test
enable signals and dealt with pin sharing while the function of Debug module is
used to multiplex function block outputs and DFT object outputs.
Clock Manage Module:
The function of Clock_mng Module is integrated all of external clock and
internal clock signals and used to multiplex normal clocks and test clocks.
Reset Manage Module:
The function of Reset_mng Module is integrated all of software Set/Reset and
hardware Set/Reset signals and used to multiplex normal set/resets and test
resets.
To ease integration to arrange the Mode Generation Module in level 1,and the
Debug Module、Clock Manage Module and Reset Manage Module in level 2 of
the design hierarchy.
The DFT integration architecture should follow the suggestions below:
To accommodate the different test requirements, mode generator and multiple test architecture must be provided on the same test design.
In order to observe the boundary signals of a specific building block in normal
mode or test output signals in different test modes , the plan must be provided to
enable debugging function flexibility
When the I/O pin count is a limited design resource, the test pins used in DFT implementation should be shared with the chip function pins.
The shared pins will be applied to DFT control signals or data input/output signals.
The shared pins could be input、output or bi-directional pins
If the shared pins as bi-directional pins should be controlled to place in the input
status or output status.
The test clock and test reset signals should be easily controllable.
There are four main blocks added in the integration architecture, Mode Generation
Module, Debug Module, Clock Manage Module and Reset Manage Module.
Mode Generation Module and Debug Module:
The function of Mode Generation Module is mainly used to generate test
enable signals and dealt with pin sharing while the function of Debug module is
used to multiplex function block outputs and DFT object outputs.
Clock Manage Module:
The function of Clock_mng Module is integrated all of external clock and
internal clock signals and used to multiplex normal clocks and test clocks.
Reset Manage Module:
The function of Reset_mng Module is integrated all of software Set/Reset and
hardware Set/Reset signals and used to multiplex normal set/resets and test
resets.
To ease integration to arrange the Mode Generation Module in level 1,and the
Debug Module、Clock Manage Module and Reset Manage Module in level 2 of
the design hierarchy.
2011年8月9日 星期二
DFT再了解(九)
How many test signals does DFT need?
test_clock :
The normal function clock(s) would be used as test_clock(s).
Test clock should be planned for ATPG operation.
Minimize usage of internally-derived clock signals.
Avoid using bi-directional ports as test_clock.
test_reset :
Make DUT easy to reset No complex initialization.
Prefer a plain asynchronous reset at primary input port.
scan_test & scan_enable :
Avoid using shared pin(s) for scan_mode and scan_enable.
If shared pin(s) is used for scan_enable or scan_mode, The function
patterns with conflict of mode switching, the fault coverage will
degrade.
It is best to have two extra input pins(dedicated pins). One is for
scan_mode and the other is for scan_enable.
Avoid using bi-directional ports as scan_mode and scan_enable.
scan_in & scan_out :
To minimize package pins ,the scan input/output pins can be shared
with the function input/output pins pads.
test_clock :
The normal function clock(s) would be used as test_clock(s).
Test clock should be planned for ATPG operation.
Minimize usage of internally-derived clock signals.
Avoid using bi-directional ports as test_clock.
test_reset :
Make DUT easy to reset No complex initialization.
Prefer a plain asynchronous reset at primary input port.
scan_test & scan_enable :
Avoid using shared pin(s) for scan_mode and scan_enable.
If shared pin(s) is used for scan_enable or scan_mode, The function
patterns with conflict of mode switching, the fault coverage will
degrade.
It is best to have two extra input pins(dedicated pins). One is for
scan_mode and the other is for scan_enable.
Avoid using bi-directional ports as scan_mode and scan_enable.
scan_in & scan_out :
To minimize package pins ,the scan input/output pins can be shared
with the function input/output pins pads.
Design Compiler再了解(四十三)
Ideal Network的使用與限制
限制
For scan-enable can’t use set_ideal_network
because this will prevent insert_dft from
hooking up the scan-enable signals.
使用範例
create_clock –period 2.5 [get_ports clk]
set_clock_uncertainty -setup 0.3 [get_clocks clk]
set_clock_transition 0.2 [get_clocks clk]
...
# Disable timing/DRC optimization of HFN Port sources
set_ideal_network [get_ports reset* select*]
# Disable timing/DRC optimization of HFN Pin sources if
# GTECH pin names and/or net names are known
set_ideal_network [get_pins FF_SET_reg/Q]
set_ideal_network –no_propagate [get_nets CTRL]
# Optional replacement values for default zero delay and
#transition values of ideal networks
#如果認為此處需要有一些delay才設定
set_ideal_latency 1.4 [get_ports reset* select*]
set_ideal_transition 0.5 [get_pins FF_SET_reg/Q]
參考轉貼
http://chipdesigns.blogspot.com/2008/12/setidealnetwork-setdonttouchnetwork.html
set_ideal_network用来对port，pin，net来设置ideal_network属性，所谓的ideal_network属性 就是0电阻0电容+所有的cell和net都dont_touch。因此就会0转换时间，0延时，综合优化的时候不会对路径的cell和net进行优化。
注 意：
1.对net进行设置的时候，必须要带上no_propagate的属性，否则是加不上去的。对port和pin可以加上带也可以不带 no_propagate。
2.当ideal_network经过一个组合logic的时候，只有当所有的输入都具有ideal属性，并且至少有一半具有 传播的属性，即不带-no_propagate，输出端才有ideal_net属性。
3.在定义时钟的时候，默认是具有这个属性的，但是要注意的是，当时 钟网络上具有多输入组合逻辑的时候，时钟的ideal_net属性是不会穿过这个组合逻辑的。比如一个2in1 mux，输出端就不具备ideal_net属性，延时就会计算进去。所以定义时钟的时候最好还是加上这条命令。
限制
For scan-enable can’t use set_ideal_network
because this will prevent insert_dft from
hooking up the scan-enable signals.
使用範例
create_clock –period 2.5 [get_ports clk]
set_clock_uncertainty -setup 0.3 [get_clocks clk]
set_clock_transition 0.2 [get_clocks clk]
...
# Disable timing/DRC optimization of HFN Port sources
set_ideal_network [get_ports reset* select*]
# Disable timing/DRC optimization of HFN Pin sources if
# GTECH pin names and/or net names are known
set_ideal_network [get_pins FF_SET_reg/Q]
set_ideal_network –no_propagate [get_nets CTRL]
# Optional replacement values for default zero delay and
#transition values of ideal networks
#如果認為此處需要有一些delay才設定
set_ideal_latency 1.4 [get_ports reset* select*]
set_ideal_transition 0.5 [get_pins FF_SET_reg/Q]
參考轉貼
http://chipdesigns.blogspot.com/2008/12/setidealnetwork-setdonttouchnetwork.html
set_ideal_network用来对port，pin，net来设置ideal_network属性，所谓的ideal_network属性 就是0电阻0电容+所有的cell和net都dont_touch。因此就会0转换时间，0延时，综合优化的时候不会对路径的cell和net进行优化。
注 意：
1.对net进行设置的时候，必须要带上no_propagate的属性，否则是加不上去的。对port和pin可以加上带也可以不带 no_propagate。
2.当ideal_network经过一个组合logic的时候，只有当所有的输入都具有ideal属性，并且至少有一半具有 传播的属性，即不带-no_propagate，输出端才有ideal_net属性。
3.在定义时钟的时候，默认是具有这个属性的，但是要注意的是，当时 钟网络上具有多输入组合逻辑的时候，时钟的ideal_net属性是不会穿过这个组合逻辑的。比如一个2in1 mux，输出端就不具备ideal_net属性，延时就会计算进去。所以定义时钟的时候最好还是加上这条命令。
Design Compiler再了解(四十二)
Parallel Synthesis using ACS –Automated Chip Synthesis
注意此用法需要多個DC license和多CPU
好處 可以平行合成跟最佳化
用途 在大型的design 上，可以只重合改過的部份
參考用法 用下面指令查詢
help acs*
printvar acs*
如果整個流程是沒有錯誤，用 acs_write_html會產生ACS HTML
整個流程的參考指令如下
第一階段
# Ensure efficient partitioning for synthesis 1
# Avoid uniquify-ing multiply-instantiated designs if possible 2
group | ungroup
# Create path groups for I/O/combo paths if I/O constraints are not accurate
group_path –critical range <10% of max delay> -weight 5|2|1
# Enable Ultra if multiple Ultra + DW licenses are available: 3
acs_set_attribute UltraOptimization true
acs_set_attribute CompileUltra true
set_compile_partitions –auto|–designs|-level –force 4
acs_set_attribute TestReadyCompile true
acs_set_attribute FullCompile high
acs_compile_design –force
# Continue if NOT meeting timing
第二階段
acs_recompile_design; # For significant timing violations
acs_refine_design; # For small timing violations
# Continue if NOT meeting timing
# Change partitioning, DRC priority and/or path group focus:
group | ungroup
set_cost_priority -delay
group_path –critical range <10% of max delay> -weight 5|2|1
# Iterate as needed
另外
# Uniquify multiple instantiations in preparation for physical design
uniquify
注意此用法需要多個DC license和多CPU
好處 可以平行合成跟最佳化
用途 在大型的design 上，可以只重合改過的部份
參考用法 用下面指令查詢
help acs*
printvar acs*
如果整個流程是沒有錯誤，用 acs_write_html會產生ACS HTML
整個流程的參考指令如下
第一階段
# Ensure efficient partitioning for synthesis 1
# Avoid uniquify-ing multiply-instantiated designs if possible 2
group | ungroup
# Create path groups for I/O/combo paths if I/O constraints are not accurate
group_path –critical range <10% of max delay> -weight 5|2|1
# Enable Ultra if multiple Ultra + DW licenses are available: 3
acs_set_attribute UltraOptimization true
acs_set_attribute CompileUltra true
set_compile_partitions –auto|–designs|-level –force 4
acs_set_attribute TestReadyCompile true
acs_set_attribute FullCompile high
acs_compile_design –force
# Continue if NOT meeting timing
第二階段
acs_recompile_design; # For significant timing violations
acs_refine_design; # For small timing violations
# Continue if NOT meeting timing
# Change partitioning, DRC priority and/or path group focus:
group | ungroup
set_cost_priority -delay
group_path –critical range <10% of max delay> -weight 5|2|1
# Iterate as needed
另外
# Uniquify multiple instantiations in preparation for physical design
uniquify
2011年8月8日 星期一
DFT再了解(八)
DFT Plan issues
How many test signals does DFT need?
Which port is scan enable (dedicate)?
Which port is scan test mode (dedicate)?
Which port is scan clock (dedicate)?
Have enough design resource to complete DFT?
If existing Bi-directional (in-out) ports? How to control them ?
What kind of coding style does DFT implementation need?
Asynchronous or synchronous design style?
How many gate clock in your design?
How many latch cells in your design?
How many macro cells in your design?
What kind of design architecture does DFT integration need ?
Mode Generation and Debug architecture
Clock architecture
Set/Reset architecture
How many scan chains? Scan chains balanceable?
What is your test coverage or fault coverage target ?
How many test signals does DFT need?
Which port is scan enable (dedicate)?
Which port is scan test mode (dedicate)?
Which port is scan clock (dedicate)?
Have enough design resource to complete DFT?
If existing Bi-directional (in-out) ports? How to control them ?
What kind of coding style does DFT implementation need?
Asynchronous or synchronous design style?
How many gate clock in your design?
How many latch cells in your design?
How many macro cells in your design?
What kind of design architecture does DFT integration need ?
Mode Generation and Debug architecture
Clock architecture
Set/Reset architecture
How many scan chains? Scan chains balanceable?
What is your test coverage or fault coverage target ?
Design Compiler再了解(四十一)
User-Defined Path Groups
假設CLK1及CLK2是最緊最需要optimial
COMBO是指此段設計在此block是combinational gates
# Example: Assign a critical range to each path group
group_path -name CLK1 -critical_range 0.3 –weight 5
group_path -name CLK2 -critical_range 0.1 –weight 5
group_path –name CLK3 –critical_range 0.2 –weight 2
group_path –name INPUTS –from [all_inputs]
group_path –name OUTPUTS –to [all_outputs]
group_path –name COMBO –from [all_inputs] –to [all_outputs]
report_path_group
一個ultra的使用例
# Apply practical auto-ungrouping settings 1
set compile_auto_ungroup_delay_num_cells
set compile_auto_ungroup_count_leaf_cells true
set compile_auto_ungroup_override_wlm true
set_ungroup false
# Create path groups for I/O/combo paths if I/O constraints are not accurate
group_path –critical range <10% of max delay> -weight 5|2|1
# If design contains pipelined sub-designs and the pipeline registers
# are grouped together at the input or output (recommended)
set_multicycle_path –setup <#stages> 2 -from|-to
# First compile
compile_ultra –scan –retime –timing|-area 3
reset_path –from|-to
# Continue if pipeline violates timing; Skip if no pipeline issues:
set_optimize_registers true –design
optimize_registers –only_attributed_designs
# Continue if design is NOT meeting all constraints:
# Apply more focus on violating critical paths
group_path –critical range <10% of max delay> -weight 5|2|1
compile_ultra –scan –incremental
另外對DesignWare有下面指令
set compile_ultra_ungroup_dw false (true by default).
假設CLK1及CLK2是最緊最需要optimial
COMBO是指此段設計在此block是combinational gates
# Example: Assign a critical range to each path group
group_path -name CLK1 -critical_range 0.3 –weight 5
group_path -name CLK2 -critical_range 0.1 –weight 5
group_path –name CLK3 –critical_range 0.2 –weight 2
group_path –name INPUTS –from [all_inputs]
group_path –name OUTPUTS –to [all_outputs]
group_path –name COMBO –from [all_inputs] –to [all_outputs]
report_path_group
一個ultra的使用例
# Apply practical auto-ungrouping settings 1
set compile_auto_ungroup_delay_num_cells
set compile_auto_ungroup_count_leaf_cells true
set compile_auto_ungroup_override_wlm true
set_ungroup
# Create path groups for I/O/combo paths if I/O constraints are not accurate
group_path –critical range <10% of max delay> -weight 5|2|1
# If design contains pipelined sub-designs and the pipeline registers
# are grouped together at the input or output (recommended)
set_multicycle_path –setup <#stages> 2 -from|-to
# First compile
compile_ultra –scan –retime –timing|-area 3
reset_path –from|-to
# Continue if pipeline violates timing; Skip if no pipeline issues:
set_optimize_registers true –design
optimize_registers –only_attributed_designs
# Continue if design is NOT meeting all constraints:
# Apply more focus on violating critical paths
group_path –critical range <10% of max delay> -weight 5|2|1
compile_ultra –scan –incremental
另外對DesignWare有下面指令
set compile_ultra_ungroup_dw false (true by default).
Design Compiler再了解(四十)
Controlling Auto-Ungrouping
# Only sub-blocks containing max_limit number of
# cells (instances), or less, will be considered for ungrouping
set compile_auto_ungroup_delay_num_cells
set compile_auto_ungroup_area_num_cells
# Prevent parent-cells from being ungrouped while the culprit
# child cells which do not meet the num_cells limit remain grouped
set compile_auto_ungroup_count_leaf_cells true
# Ensure that sub-blocks with WLMs that are different
# than their parent cell are allowed to be ungrouped
set compile_auto_ungroup_override_wlm true
# Prevent glue logic at the top level of your current design
# or maintain the hierarchy of key blocks, e.g. for verification, pipeline designs
set_ungroup false
To achieve the best synthesis results set max_limitto
‘infinite’, e.g. 99,999,999
May lose significant hierarchy in the design –
consider post-synthesis simulation and physical layout affects
Apply smaller limit if needed or control with set_ungroup false
# Only sub-blocks containing max_limit number of
# cells (instances), or less, will be considered for ungrouping
set compile_auto_ungroup_delay_num_cells
set compile_auto_ungroup_area_num_cells
# Prevent parent-cells from being ungrouped while the culprit
# child cells which do not meet the num_cells limit remain grouped
set compile_auto_ungroup_count_leaf_cells true
# Ensure that sub-blocks with WLMs that are different
# than their parent cell are allowed to be ungrouped
set compile_auto_ungroup_override_wlm true
# Prevent glue logic at the top level of your current design
# or maintain the hierarchy of key blocks, e.g. for verification, pipeline designs
set_ungroup
To achieve the best synthesis results set max_limitto
‘infinite’, e.g. 99,999,999
May lose significant hierarchy in the design –
consider post-synthesis simulation and physical layout affects
Apply smaller limit if needed or control with set_ungroup false
2011年8月7日 星期日
TCL 基本指令
參考網址
http://www.dev.idv.tw/mediawiki/index.php/Tcl%E7%9A%84%E8%AE%8A%E6%95%B8%E4%BB%8B%E7%B4%B9
http://www.hume.com/html84/
http://blog.got7.org/2009/06/6tcl.html
lappend search_path bob
相對其它的方法
set search_path “$search_path bob”
set search_path [concat $search_path bob]
http://www.dev.idv.tw/mediawiki/index.php/Tcl%E7%9A%84%E8%AE%8A%E6%95%B8%E4%BB%8B%E7%B4%B9
http://www.hume.com/html84/
http://blog.got7.org/2009/06/6tcl.html
- list 根據給定的參數製作對應的串列。
- lindex 從串列中取得指定的項目。
- lappend 新增一個項目到指定的串列中。
- linsert 插入一個項目至串列中的某個位置。
- llength 計算串列中項目的總數。
- lrange 取出某個範圍的子串列。
- lreplace 將串列某個範圍的項目置換成新的項目。
- lsearch 搜尋某個項目在串列中的位置。
- lsort 對串列進行排序。
- join 將串列合併為一個字串。
- split 分割字串成為串列。
lappend search_path bob
相對其它的方法
set search_path “$search_path bob”
set search_path [concat $search_path bob]
DFT再了解(七)
根據各種做法去 performs
scan chain extraction 或
scan cell replacement and scan chain synthesis 或
Scan synthesis achieved by taking RTL directly to a scan synthesized design
然後
DFT DRCs in preparation
for TetraMAX ATPG
DFT 整個流程 可參考下面各圖
1. read verilog or ddc file, and then Scan insertion is
performed on mapped designs
2. Create Test Protocol
A. The Test Protocol describes how the
design operates in scan mode
B. Signals involved in the protocol are
declared with the set_dft_signal command
C. The protocol is created by the
create_test_protocol command
3. DFT DRC
A. The dft_drc command performs
DRC checks prior to scan insertion
B. DRC violations can be debugged
graphically with DesignVision or
fixed by DFT Compiler with Autofix
4. Specify Scan Architecture
A. Various commands control the scan
architecture (number of scan chains, how
clock domain are handled, etc.)
B. The commands primarily used to
control the scan architecture are the
set_scan_configuration and set_scan_path
commands
5. Preview
A. The preview_dft command is used to
get a preview of the scan architecture
before it is actually implemented in the design
B. The preview step allows for a quicker
iteration cycles when changes need
to be made to the scan architecture
6. Insert Scan Paths
The scan architecture is inserted into the
design by the insert_dft command
7. DFT DRC Coverage
A. DFT DRC checks can also be run after
scan insertion to validate that the
scan chains trace properly
B. DFT DRC can also be used to get an
ATPG coverage estimate for the scan
inserted design
8. Handoff Design
A. The design handoff is where files are written
to disk that will be needed later on in the design process
B. Examples: design DDC, verilog netlist,
protocol file (for TetraMAX), Test Model (for Bottom-Up
flows), SCANDEF (for backend scan chain reordering), etc.
scan chain extraction 或
scan cell replacement and scan chain synthesis 或
Scan synthesis achieved by taking RTL directly to a scan synthesized design
然後
DFT DRCs in preparation
for TetraMAX ATPG
DFT 整個流程 可參考下面各圖
1. read verilog or ddc file, and then Scan insertion is
performed on mapped designs
2. Create Test Protocol
A. The Test Protocol describes how the
design operates in scan mode
B. Signals involved in the protocol are
declared with the set_dft_signal command
C. The protocol is created by the
create_test_protocol command
3. DFT DRC
A. The dft_drc command performs
DRC checks prior to scan insertion
B. DRC violations can be debugged
graphically with DesignVision or
fixed by DFT Compiler with Autofix
4. Specify Scan Architecture
A. Various commands control the scan
architecture (number of scan chains, how
clock domain are handled, etc.)
B. The commands primarily used to
control the scan architecture are the
set_scan_configuration and set_scan_path
commands
5. Preview
A. The preview_dft command is used to
get a preview of the scan architecture
before it is actually implemented in the design
B. The preview step allows for a quicker
iteration cycles when changes need
to be made to the scan architecture
6. Insert Scan Paths
The scan architecture is inserted into the
design by the insert_dft command
7. DFT DRC Coverage
A. DFT DRC checks can also be run after
scan insertion to validate that the
scan chains trace properly
B. DFT DRC can also be used to get an
ATPG coverage estimate for the scan
inserted design
8. Handoff Design
A. The design handoff is where files are written
to disk that will be needed later on in the design process
B. Examples: design DDC, verilog netlist,
protocol file (for TetraMAX), Test Model (for Bottom-Up
flows), SCANDEF (for backend scan chain reordering), etc.
Design Compiler再了解(三十九)
pipeline design在DC
If your design is timing-critical and non-pipeline registers
are allowed to be re-positioned, invoke adaptive retiming
compile_ultra –scan –retime -timing
If you have pipelined sub-design(s) invoke register
repositioning to optimize your pipeline
optimize_registers
用法如下
先看design
data <= a*b + c*d + e-f;
always @ (posedge clk)
begin
R1 <= data;
R2 <= R1;
R3 <= R2;
再看constraint
current_design Top_Design
# Relax pipeline timing requirement for initial compile
set_multicycle_path –setup 3 –to U_Pipeline/R1_reg*
# First compile
compile_ultra –scan –retime –timing
# Reset pipeline timing back to the original constraints
reset_path -to U_Pipeline/R1_reg*
# Continue if pipeline violates timing; Skip if no pipeline issues:
set_dont_touch [get_cells U_Pipeline/R3_reg*] true
set_optimize_registers true –design Pipeline
optimize_registers –only_attributed_designs
結果如下
If your design is timing-critical and non-pipeline registers
are allowed to be re-positioned, invoke adaptive retiming
compile_ultra –scan –retime -timing
If you have pipelined sub-design(s) invoke register
repositioning to optimize your pipeline
optimize_registers
用法如下
先看design
data <= a*b + c*d + e-f;
always @ (posedge clk)
begin
R1 <= data;
R2 <= R1;
R3 <= R2;
再看constraint
current_design Top_Design
# Relax pipeline timing requirement for initial compile
set_multicycle_path –setup 3 –to U_Pipeline/R1_reg*
# First compile
compile_ultra –scan –retime –timing
# Reset pipeline timing back to the original constraints
reset_path -to U_Pipeline/R1_reg*
# Continue if pipeline violates timing; Skip if no pipeline issues:
set_dont_touch [get_cells U_Pipeline/R3_reg*] true
set_optimize_registers true –design Pipeline
optimize_registers –only_attributed_designs
結果如下
Design Compiler再了解(三十八A)
Multi-cycle PATH的基本用法
set_multicycle_path -setup 6 -to C_reg[*]
set_multicycle_path -hold 5 -to C_reg[*]
特殊的design下
因為有不同的path所以要特別的指定路徑
set_multicycle_path –setup 2 –from A_reg/clocked_on \
-through U_Mult/Out –to B_reg/next_state
set_multicycle_path –hold 1 –from A_reg/clocked_on \
-through U_Mult/Out –to B_reg/next_state
set_multicycle_path -setup 6 -to C_reg[*]
set_multicycle_path -hold 5 -to C_reg[*]
特殊的design下
因為有不同的path所以要特別的指定路徑
set_multicycle_path –setup 2 –from A_reg/clocked_on \
-through U_Mult/Out –to B_reg/next_state
set_multicycle_path –hold 1 –from A_reg/clocked_on \
-through U_Mult/Out –to B_reg/next_state
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