PrimeTime再了解(一)

作为专门的静态时序分析工具，PrimeTime 可以为一个设计提供以下的时序分
析和设计检查

1 建立和保持时间的检查(setup and hold checks)
2 时钟脉冲宽度的检查
3 时钟门的检查(clock-gating checks)
4 recovery and removal checks
5 unclocked registers
6 未约束的时序端点（unconstrained timing endpoints）
7 master-slave clock separation
8 multiple clocked registers
9 组合反馈回路（combinational feedback loops）
10 基于设计规则的检查，包括对最大电容、最大传输时间、最大扇出的检查

Milkway library

用MilkeyWay这个软件做一个MW的库出来，这个库就是你的Reference Libararyj

Front End only design, there is no need for mw library if you have db file, which is good enough.
Back End desing, you need the phyiscal information, which stores in mw library.

You can use "Milkyway" or "Astro" to generate the mw library. The "gePrepLibs" is the scheme command which can be used under both tools. icc_shell won't accept that. icc_shell don't use scheme language.

You can have options to use .lib or .db for LM view.

The LM (logic model) view minimizes the transfer of data between the standard Synopsys design database and the Milkyway database, providing integration of the two Synopsys databases.
The LM view is derived from the .lib- or .db-formatted Synopsys libraries. It resides in the Milkyway reference library directory structure, enabling Astro to use the same timing information as Design Compiler and Physical Compiler and the same cell delay calculator as PrimeTime. The LM view supports the same net delay calculator as PrimeTime, and it has better correlation with PrimeTime than the TIM view.

The LM view provides enhanced SDC correlation and enhanced Astro-Rail support. It also adds logical library capability to Astro. In addition, the Astro-Rail-to-Power Compiler flow and the read- and write Milkyway database processes (from Design Compiler and Physical Compiler) require LM views.

ICC初探(一)

ICC的步骤就是开始一个design，必须对这个design先建立milkyway library。这个milkyway library指的就是你当前的design的database，当你完成当前design的P&R后，此library就包含了你的 design的所有layout信息如fp，placement，routing等等。

而target library，link library指的是你的design要调用的stdcell，memory，IP的timing信息

milkyway reference library指的就是你所调用的stdcell、memory、IP的physical 信息，一般有framview，cellview等等。 framview一般只包含IO pin信息，而cellview包含了很详细的PR信息。

SVA 再了解(十)

bind的使用

先看一下bind的語法

先寫一個給bind用的module
module mutex_chk(a, b, elk);
input logic a, b, elk;

property p_mutex;
©(posedge elk) not (a && b);
endproperty

a_mutex: assert property{p_mutex);
endmodule

假如有一個design如下
module t o p {. . ) ;
inline ul (elk, a, b, inl, in2, outl);
inline u2 (elk, c, d, in3, in4, out2);
endmodule

我們可以在design上加入下面的bind作check
bind top.ul mutex_ehk il(a, b, elk);
bind top.u2 mutex_ehk i2(c, d, elk);

SVA 再了解(九)

SVA for Data Integrity in Asynchronous FIFO

int wcnt, rcnt;
always @(posedge wclk) if (write) wcnt = wcnt + 1;
always @(posedge rclk) if (read) rcnt = rcnt + 1;
property p_data_integrity;
int cnt;
logic data;
@(posedge wclk)
(write, cnt=wcnt, data=wdata) |=>
@(posedge rclk)
first_match(##[0:$] (read & (rcnt==cnt))) //$盡量不要用，會拖慢模擬速度
##0 (rdata==data);
endproperty

assert property (p_data_integrity);

UVM Register(十七)

一個uvm_reg_file的使用範例在SESSION Reg的定義


//先定義SOCKET，這是一個64bits的socket
class reg_slave_SOCKET extends uvm_reg;

rand uvm_reg_field IP;
rand uvm_reg_field PORT;

function new(string name = "slave_ADDR");
super.new(name,64,UVM_NO_COVERAGE);
endfunction: new

virtual function void build();
this.IP = uvm_reg_field::type_id::create("IP");
this.PORT = uvm_reg_field::type_id::create("PORT");

this.IP.configure(this, 48, 0, "RW", 0, 48'h0, 1, 0, 1);
this.PORT.configure(this, 16, 48, "RW", 0, 16'h0, 1, 0, 1);
endfunction

`uvm_object_utils(reg_slave_SOCKET)

endclass


class reg_slave_SESSION extends uvm_reg_file;

rand reg_slave_SOCKET SRC;
rand reg_slave_SOCKET DST;

function new(string name = "slave_SESSION");
super.new(name);
endfunction: new

virtual function void build();
this.SRC = reg_slave_SOCKET::type_id::create("SRC");
this.DST = reg_slave_SOCKET::type_id::create("DST");

this.SRC.configure(get_block(), this, "SRC");//這個get_block()會傳回這個block parent
this.DST.configure(get_block(), this, "DST");

this.SRC.build();
this.DST.build();
endfunction

//這個map並非uvm_reg_file內定的function，
//所以是要給其它的class來呼叫
virtual function void map(uvm_reg_map mp,
uvm_reg_addr_t offset);
mp.add_reg(SRC, offset+'h00);
mp.add_reg(DST, offset+'h08);
endfunction

virtual function void set_offset(uvm_reg_map mp,
uvm_reg_addr_t offset);
SRC.set_offset(mp, offset+'h00);
DST.set_offset(mp, offset+'h08);
endfunction

`uvm_object_utils(reg_slave_SESSION)

endclass


使用SESSION的uvm_reg_block範例
class reg_block_slave extends uvm_reg_block;

reg_slave_ID ID;
reg_slave_INDEX INDEX;
reg_slave_DATA DATA;

rand reg_slave_SESSION SESSION[256]; // array style

rand reg_slave_TABLES TABLES[256];

mem_slave_DMA_RAM DMA_RAM;

uvm_reg_field REVISION_ID;
uvm_reg_field CHIP_ID;
uvm_reg_field PRODUCT_ID;

function new(string name = "slave");
super.new(name,UVM_NO_COVERAGE);
endfunction

virtual function void build();

// create
ID = reg_slave_ID::type_id::create("ID");
INDEX = reg_slave_INDEX::type_id::create("INDEX");
DATA = reg_slave_DATA::type_id::create("DATA");
foreach (SESSION[i])
SESSION[i] = reg_slave_SESSION::type_id::create($sformatf("SESSION[%0d]",i));
foreach (TABLES[i])
TABLES[i] = reg_slave_TABLES::type_id::create($sformatf("TABLES[%0d]",i));
DMA_RAM = mem_slave_DMA_RAM::type_id::create("DMA_RAM");

// configure
ID.configure(this,null,"ID");
ID.build();
INDEX.configure(this,null,"INDEX");
INDEX.build();
foreach (SESSION[i]) begin
SESSION[i].configure(this,null,$sformatf("SESSION[%0d]",i));
SESSION[i].build();
end
foreach (TABLES[i]) begin
TABLES[i].configure(this,null,$sformatf("TABLES[%0d]",i));
TABLES[i].build();
end
// the SV LRM IEEE2009 is not clear if an array of class handles can be assigned to another array if the element types
// are assignment compatible OR if the LRM states the element types have to be 'equal' (the LRM states equal types)
// IUS requires per LRM 'equivalent' element types and does not accept assignment compatible types
`ifdef INCA
begin
uvm_reg r[256];
foreach(TABLES[i])
r[i]=TABLES[i];

DATA.configure(INDEX, r, this, null);
end
`else
DATA.configure(INDEX, TABLES, this, null);
`endif

DATA.build();

DMA_RAM.configure(this,"");

// define default map
default_map = create_map("default_map", 'h0, 4, UVM_LITTLE_ENDIAN);
default_map.add_reg(ID, 'h0, "RW");
default_map.add_reg(INDEX, 'h20, "RW");
default_map.add_reg(DATA, 'h24, "RW");
foreach (SESSION[i])
SESSION[i].map(default_map, 'h1000 + 16 * i);

default_map.add_mem(DMA_RAM, 'h2000, "RW");

// field handle aliases
REVISION_ID = ID.REVISION_ID;
CHIP_ID = ID.CHIP_ID;
PRODUCT_ID = ID.PRODUCT_ID;
endfunction

`uvm_object_utils(reg_block_slave)

endclass : reg_block_slave

System Generator in Xilinx and Matlab

软件要求
fMATLAB v7.0.1/Simulink v6.1 (R14.1) Service Pack 1, MATLAB
v7.0.4/Simulink v6.2 (R14.2)Service Pack 2, or MATLAB
v7.1.0/Simulink v6.3 (R14.3),
fXilinx ISE Foundation or Alliance, release version v8.1.01 (8.1
Service Pack 1) or later.

软硬件安装
f硬件方面: 安装好FPGA开发板
f软件方面: 安装好Systemgen后,可以再下载新的 plugin 来支持更
多的板卡,安装方法
y 下载相应的plugin
y 在matlab中,把当前目录设置到plugin的位置
y 在matlab里面输入 xlInstallPlugin(‘myplugin.zip’)


System Generator 的基本特性
支持VHDL和Verilog的自动代码生成
支持软硬件协同仿真
支持网络方式和以太网方式
支持Xilinx的开发工具
f与EDK交互
f对硬件自动综合和软件接口的抽象
f自动生成对外设和协处理器的抽象
f生成RTL
f对Simulink集成
f使用黑盒子插入VHDL和Verilog

CHIP/IP ID Register 在Design上的使用

一個reuse的IP/platform/product在Design通常有一組記錄ID的Register
因為在Chip整合時，需要將所使用到的IP/platform列出在這顆Chip上所
用到的整合表單，因此ID可以表示出目前所用到的版本，在出Chip時，
我們所用到的IP通常不會是Full function或是最新的，因此在ID Register上
我們可以展示出所用到的版本，及所用的define組合的代號，整合或系統測
試時，只要讀到這個ID Register就可以對照Design Spec.的表格去作整合模擬與
測試。以下是一個ID Register的範例，Product_ID在IP/platform上可以代表所用的
define組合，Chip_ID可以代表IP/Platform的數字代碼，
REVISION_ID可以代表改版的代號。

uvm_cmdline_processor的使用範例

有點類似$value$plusargs
請參考http://kirenenko-tw.blogspot.com/2011/05/valueplusargs.html

// run shell example

hw_reset:
$(IUS) -incdir ../../../integrated/apb tb_top.sv test.sv \
+UVM_TESTNAME=cmdline_test +UVM_REG_SEQ=uvm_reg_hw_reset_seq
$(CHECK)


//--------------- UVM example code--------------------
uvm_cmdline_processor opts = uvm_cmdline_processor::get_inst();

uvm_reg_sequence seq;
string seq_name;

void'(opts.get_arg_value("+UVM_REG_SEQ=", seq_name));

$display ("\n\n My test = %s\n\n", seq_name);


//--------------- sim result -------------------------
My test = uvm_reg_hw_reset_seq

How the Test Plan Relates to Functional Coverage

一個大概的範例

Design and Verification Team Considerations

Designers should embed their assertions in the design near the RTL that’s
being tested.
– Easy to capture assumptions, expectations, and identify corner cases as the code is
written
– Makes good documentation
• Interface assertions should be in a verification component for reuse.
– The verification components can be instantiated in the test bench, or in an external
file.
• Verification engineers should use external files for their assertions.
– Avoids conflicts with the designer
– Easily separated
• Place coverage points in an external file or within an `ifdef directive.
– This allows the user to avoid the performance impact when coverage is not used.

SVA 再了解(八)

將SVA嵌入到Verilog design裡的一個例子

typedef 在class上輸入的變數

class uvm_rgm_sfld_register #(int SIZE = 32,
string RAP = "REG_RD",
string WAP = "REG_WR")
extends uvm_rgm_sized_register#(SIZE);
...

class uvm_rgm_sized_register #(int SIZE=32) extends uvm_rgm_register_base;

typedef bit[SIZE-1:0] this_register_type;

....

// User register
typedef uvm_rgm_sfld_register#(16) user_reg;
將user_reg上對映的SIZE大小設為16

SVA 再了解(七)

$onehot() 與$onehot0()的例子

property OH;
@(posedge CLK)
($onehot(GRANT_VEC));
endproperty

property OH_ZERO;
@(posedge CLK)
($onehot0(GRANT_VEC));
endproperty

SVA 再了解(六)

一個檢查pipe的SVA例子

DATA_PIPELINE: assert property (
@(posedge clk) disable iff(!rst_n)
$rose(valid) |-> (##5 pipe_ready ##1 pipe3_data==$past(port_data, 2)
);