UNIX Structure of a Milkyway Libraries

Reference libraries are Milkyway databases, with a similar
UNIX structure as a design library database.

Reference libraries contain different views:
CEL: The full layout view
FRAM: The abstract view used for P&R, as well as DC Topographical
LM: Logic Model with Timing and Power info, used by layout tools














The timing and power information of the LM views is not used by DC Topographical – it gets its
timing (and if applicable, power) information from the target and link libraries.

The full layout (CEL) view is used after Placement and Routing (P & R) are completed, and the
design is ready to be “taped out”. This means that the full layout representation of the design is
written out in a standard format called GDSII – this file must contain ALL the physical data of
the design, not just the “abstract” data used during P & R.

Milkyway Reference and Design Libraries

Target and link libraries must still be specified for
logical, timing and power info


The reference libraries (standard cell and, if applicable, macro cell or IP libraries), along with the
technology file and TLU-plus file (if applicable) are all provided by the back-end vendor or library group.

The arrow from the reference libraries is dashed to indicate that the reference libraries are not
included in the design library – instead, the design library contains a “pointer” to the libraries.

Note: The recommended format for transferring design data between Design Compiler and
Physical Compiler or IC Compiler is ddc – not Milkyway.

For DC-to-Astro, output a Verilog netlist, along with the sdc constraints file.

Layout vs Abstract Views in Milkyway Library

A standard cell library also contains a corresponding
abstract view for each layout view

Abstract views contain only the minimal data needed
for Place & Route

















The use of abstract views instead of cell views enables smaller, more efficient design databases to be built and manipulated by P&R tools.

The abstract views do not contain underlying device details (poly, diffusion, n-wells, contacts).

They contain only the following:
- Outline of the cell (The “placement” tool places each cell in available sites in the core of the
chip. All the placer needs to know is the size and shape (outline) of the cell.)
- Pin locations and layer (Pins are usually metal connections to the underlying poly or diffusion
areas of the devices. The “router” tool uses these pin locations to route metal wires or connections
to each cell)
- Metal blockages (Areas in a cell where metal of a certain layer can not be routed because that
layer is being used in the full layout of the cell, but does not show up as a pin in the abstract view.
The example layout above is too simple to require blockages. These are more commonly needed in macro cells)

The layout and abstract views of all standard cells are built by a Library group. These cells are
usually initially built in a standard format called GDSII and then converted into tool-specific
formats (e.g. Milkyway database format for use by Synopsys tools).

Library 名詞表

- target_library : describes the cells you’re map to (.db file)

- link_library : describes cells you’ve instantiated, and any wire load or operating condition models you are using (.db file)

- symbol_library : contains symbols(.sdb file) for the GUI’s schematic viewer

- synthetic_library : contains soft macro(.sldb file) to implement math functions

- design_lib : Holds intermediate format descriptions of your HDL code for design reuse;(really just a pointer to a subdirectory)

What is a Standard Cell Library?

Standard cell libraries describe the layout of basic combinational and sequential logic gates like:
• inverters
• buffers
• ands
• ors
• nands
• nors
• muxes
• latches
• flip-flops

Standard cell libraries are generally called “reference” libraries. These reference libraries are
technology specific and are usually created and provided by an external ASIC vendor or internal
library group.

In addition to standard cell libraries, reference libraries also contain pad cell libraries for signal IO and power/ground pad cells, as well as macro cell or IP libraries for reusable IP like RAMs,
ROMs, and other predesigned, standard, complex blocks.