DFT再了解(七)

根據各種做法去 performs
scan chain extraction 或
scan cell replacement and scan chain synthesis 或
Scan synthesis achieved by taking RTL directly to a scan synthesized design

然後
DFT DRCs in preparation
for TetraMAX ATPG

DFT 整個流程 可參考下面各圖




























































1. read verilog or ddc file, and then Scan insertion is
performed on mapped designs

2. Create Test Protocol
A. The Test Protocol describes how the
design operates in scan mode
B. Signals involved in the protocol are
declared with the set_dft_signal command
C. The protocol is created by the
create_test_protocol command

3. DFT DRC
A. The dft_drc command performs
DRC checks prior to scan insertion
B. DRC violations can be debugged
graphically with DesignVision or
fixed by DFT Compiler with Autofix

4. Specify Scan Architecture
A. Various commands control the scan
architecture (number of scan chains, how
clock domain are handled, etc.)
B. The commands primarily used to
control the scan architecture are the
set_scan_configuration and set_scan_path
commands

5. Preview
A. The preview_dft command is used to
get a preview of the scan architecture
before it is actually implemented in the design
B. The preview step allows for a quicker
iteration cycles when changes need
to be made to the scan architecture

6. Insert Scan Paths
The scan architecture is inserted into the
design by the insert_dft command

7. DFT DRC Coverage
A. DFT DRC checks can also be run after
scan insertion to validate that the
scan chains trace properly
B. DFT DRC can also be used to get an
ATPG coverage estimate for the scan
inserted design

8. Handoff Design
A. The design handoff is where files are written
to disk that will be needed later on in the design process
B. Examples: design DDC, verilog netlist,
protocol file (for TetraMAX), Test Model (for Bottom-Up
flows), SCANDEF (for backend scan chain reordering), etc.