Multiple Tool Environments
DC shell also other environments – Multi-voltage mode, UPF mode, and Topographical mode.
DC shell can be run interactively or in “batch mode”.
DCT has a GUI mode called “DC Graphical”.
Design Vision (design_vision) must be used for Graphical Debug of DFT DRC violations.
IC compiler (ICC) can be used for scan chain reordering in the backend. There isn’t a “scan
insertion” flow in ICC.
2011年8月6日 星期六
Design Compiler再了解(三十八)
Multiple Clock Delay
此處只能用在 Synchronous clock 注意! 注意!
如果是 Asynchronous clock指要設false path即可
set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]
set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]
對所有的clock要設false path
可用下面語法，簡便許多
set DESIGN_CLOCKS [all_clocks]
foreach_in_collection _CLK $DESIGN_CLOCKS {
set_false_path -from $_CLK -to [remove_from_collection [all_clocks] $_CLK]
}
在Synchronous clock中必須注意的是
有些clock是virtual
所以必須要用
Use virtual clocks and –add_delay as needed
input pin/port的部分
output pin/port的部分
此處只能用在 Synchronous clock 注意! 注意!
如果是 Asynchronous clock指要設false path即可
set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]
set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]
對所有的clock要設false path
可用下面語法，簡便許多
set DESIGN_CLOCKS [all_clocks]
foreach_in_collection _CLK $DESIGN_CLOCKS {
set_false_path -from $_CLK -to [remove_from_collection [all_clocks] $_CLK]
}
在Synchronous clock中必須注意的是
有些clock是virtual
所以必須要用
Use virtual clocks and –add_delay as needed
input pin/port的部分
output pin/port的部分
Design Compiler再了解(三十七)
set_wire_load_model的使用
...
set_wire_load_model –name 1.6MGates
set_wire_load_mode enclosed
set_wire_load_model –name 800KGates [get_designs SUB1]
set_wire_load_model –name 200KGates [get_designs B1]
set_wire_load_model –name 100KGates [get_designs B2]
...
對net/pin/port的特別設定
set_wire_load_model –name 200KGates
set_wire_load_model –name 1.6MGates [get_ports {IN1 OUT1}]
set_port_fanout_number 2 [get_ports IN1]
set_port_fanout_number 4 [get_ports OUT1]
set_load 0.012 [get_ports IN1]
set_load 0.074 [get_ports OUT1]
wire load mode的設定
對Block的個別設定
current_design TOP...
set_wire_load_model –name 1.6MGates
set_wire_load_mode enclosed
set_wire_load_model –name 800KGates [get_designs SUB1]
set_wire_load_model –name 200KGates [get_designs B1]
set_wire_load_model –name 100KGates [get_designs B2]
...
對net/pin/port的特別設定
set_wire_load_model –name 200KGates
set_wire_load_model –name 1.6MGates [get_ports {IN1 OUT1}]
set_port_fanout_number 2 [get_ports IN1]
set_port_fanout_number 4 [get_ports OUT1]
set_load 0.012 [get_ports IN1]
set_load 0.074 [get_ports OUT1]
wire load mode的設定
2011年8月5日 星期五
Design Compiler再了解(三十六)
Multiple Input/Output Paths
先看input的部份
create_clock -period 2 [get_ports Clk]
set_input_delay -max 0.3 –clock Clk –clock_fall [get_ports A]
set_input_delay -max 1.2 –clock Clk –add_delay [get_ports A]
再看output的部份
multi-output delay的設法也是一樣的
set_output_delay –max 2.5 –clock Clk [get_ports B]
set_output_delay –max 0.7 –clock Clk - clock_fall –add_delay \
[get_ports B]
先看input的部份
create_clock -period 2 [get_ports Clk]
set_input_delay -max 0.3 –clock Clk –clock_fall [get_ports A]
set_input_delay -max 1.2 –clock Clk –add_delay [get_ports A]
再看output的部份
multi-output delay的設法也是一樣的
set_output_delay –max 2.5 –clock Clk [get_ports B]
set_output_delay –max 0.7 –clock Clk - clock_fall –add_delay \
[get_ports B]
DFT再了解(五)
DFT Compiler Flows Supported
Top-Down
Scan insertion is performed at the top-level for the entire
design in one step
Bottom-Up
Scan insertion is performed at the block-level and
results are later combined at the top-level
Unmapped Flow
Scan insertion begins with an unmapped (RTL) design
Mapped Flow
Scan insertion begins with a mapped (gate-level) design
Extraction (Inference)
Scan insertion begins with a design that has existing
scan chains already inserted
Top-Down
Scan insertion is performed at the top-level for the entire
design in one step
Bottom-Up
Scan insertion is performed at the block-level and
results are later combined at the top-level
Unmapped Flow
Scan insertion begins with an unmapped (RTL) design
Mapped Flow
Scan insertion begins with a mapped (gate-level) design
Extraction (Inference)
Scan insertion begins with a design that has existing
scan chains already inserted
2011年8月4日 星期四
Design Compiler再了解(三十五)
create_clock的特殊用法
不建議的用法
The -waveform option should be used only to modify the duty-cycle and/or invert the waveform. To introduce an offset it is recommended to use set_clock_latency.
另外的特殊定義模式
不建議的用法
The -waveform option should be used only to modify the duty-cycle and/or invert the waveform. To introduce an offset it is recommended to use set_clock_latency.
另外的特殊定義模式
Design Compiler再了解(三十四)
report_timing的基本與特殊用法
如果要報出所有violation就用 report_constraint –all
to determine all the constraint violations in your design
否則就用report_timing來報出想要看的部份
A. Breaks the design down into individual timing paths
B. Analyzes each timing path at least twice for single-cycle
max-delay timing
Rising endpoint and falling endpoint
C. Generates a default, four-section report which includes:
One path, the worst violator 1 , per path group 2
Maximum delay or setup timing only
No hold timing
No DRC
No area
1 The worst violator is defined as the path with the largest or worst negative slack (WNS). If a
clock group has no violating paths then the path with the smallest positive slack is reported.
2 A path group is a group of timing paths which are all captured by the same clock, by default. In a later Unit user-defined path groups will be discussed.
report_timing
[ -delay max/min ]
[ -to pin_port_clock_list ]
[ -from pin_port_clock_list ]
[ -through pin_port_list ]
[ -group]
[ -input_pins ]
[ -max_paths path_count ]
[ -nworst paths_per_endpoint_count ]
[ -nets ]
[ -capacitance ]
[ -significant_digits number ]
report_timing -input_pins -significant_digits 6
This option shows the delay of the net connected to the input pin.
Point Incr Path
--------------------------------------------------------------------------
I_PRGRM_DECODE/U362/A (buf1a2) 0.000246 2.040246 f
report_timing -nets
The option shows the net name and the fanout, it does not report the delay.
Point Fanout Incr Path
--------------------------------------------------------------------------
I_PRGRM_DECODE/Crnt_Instrn[25] (net) 0.00 2.04 f
I_PRGRM_DECODE/n984 (net) 4 0.00 2.53 f
Since all 4 paths are part of the same path group, only one path, the path with the worst negative
slack (WNS) of -0.3 is reported with a default report_timing.
report_timing-max_paths 2
will generate two worst slack reports, but only allowing one
path per endpoint. In this example it will give you the paths with Slack = -0.3 and Slack = -0.15.
report_timing -max_paths 2 -nworst 2
will generate two worst slack reports, but
this time allowing up to two paths per endpoint. In this example it will give you the paths with
Slack = -0.3 and Slack = -0.25.
另外
report_timing -through {U1/a U3/a}
report_timing -through {U1/b U3/a}
可以變成
report_timing -through {U1/a U1/b} -through {U3/a}
如果要報出所有violation就用 report_constraint –all
to determine all the constraint violations in your design
否則就用report_timing來報出想要看的部份
A. Breaks the design down into individual timing paths
B. Analyzes each timing path at least twice for single-cycle
max-delay timing
Rising endpoint and falling endpoint
C. Generates a default, four-section report which includes:
One path, the worst violator 1 , per path group 2
Maximum delay or setup timing only
No hold timing
No DRC
No area
1 The worst violator is defined as the path with the largest or worst negative slack (WNS). If a
clock group has no violating paths then the path with the smallest positive slack is reported.
2 A path group is a group of timing paths which are all captured by the same clock, by default. In a later Unit user-defined path groups will be discussed.
report_timing
[ -delay max/min ]
[ -to pin_port_clock_list ]
[ -from pin_port_clock_list ]
[ -through pin_port_list ]
[ -group]
[ -input_pins ]
[ -max_paths path_count ]
[ -nworst paths_per_endpoint_count ]
[ -nets ]
[ -capacitance ]
[ -significant_digits number ]
report_timing -input_pins -significant_digits 6
This option shows the delay of the net connected to the input pin.
Point Incr Path
--------------------------------------------------------------------------
I_PRGRM_DECODE/U362/A (buf1a2) 0.000246 2.040246 f
report_timing -nets
The option shows the net name and the fanout, it does not report the delay.
Point Fanout Incr Path
--------------------------------------------------------------------------
I_PRGRM_DECODE/Crnt_Instrn[25] (net) 0.00 2.04 f
I_PRGRM_DECODE/n984 (net) 4 0.00 2.53 f
Since all 4 paths are part of the same path group, only one path, the path with the worst negative
slack (WNS) of -0.3 is reported with a default report_timing.
report_timing-max_paths 2
will generate two worst slack reports, but only allowing one
path per endpoint. In this example it will give you the paths with Slack = -0.3 and Slack = -0.15.
report_timing -max_paths 2 -nworst 2
will generate two worst slack reports, but
this time allowing up to two paths per endpoint. In this example it will give you the paths with
Slack = -0.3 and Slack = -0.25.
另外
report_timing -through {U1/a U3/a}
report_timing -through {U1/b U3/a}
可以變成
report_timing -through {U1/a U1/b} -through {U3/a}
DFT再了解(四)
Ad Hoc DFT
Adding testability logic at designer’s discretion
Example: control points or observe points
Other examples: bus keepers or pull-up resistors
Location and type left up to designer’s DFT savvy
As SoC designs adopt more kinds of on-chip logic, however, there is a competing trend.
Embedded memories, IP cores, and on-chip analog blocks all present diverse test needs.
Making these different kinds of circuits testable often requires ad hoc DFT techniques.
Test-point logic is nonfunctional—that is, not a requisite part of on-chip application logic.
Adding it to the chip represents overhead, but can provide large gains in testability.
Conclusion:
You will need to utilize both structured and ad hoc DFT to meet SOC test requirements.
Adding testability logic at designer’s discretion
Example: control points or observe points
Other examples: bus keepers or pull-up resistors
Location and type left up to designer’s DFT savvy
As SoC designs adopt more kinds of on-chip logic, however, there is a competing trend.
Embedded memories, IP cores, and on-chip analog blocks all present diverse test needs.
Making these different kinds of circuits testable often requires ad hoc DFT techniques.
Test-point logic is nonfunctional—that is, not a requisite part of on-chip application logic.
Adding it to the chip represents overhead, but can provide large gains in testability.
Conclusion:
You will need to utilize both structured and ad hoc DFT to meet SOC test requirements.
2011年8月3日 星期三
UNIX Structure of a Milkyway Libraries
Reference libraries are Milkyway databases, with a similar
UNIX structure as a design library database.
Reference libraries contain different views:
CEL: The full layout view
FRAM: The abstract view used for P&R, as well as DC Topographical
LM: Logic Model with Timing and Power info, used by layout tools
The timing and power information of the LM views is not used by DC Topographical – it gets its
timing (and if applicable, power) information from the target and link libraries.
The full layout (CEL) view is used after Placement and Routing (P & R) are completed, and the
design is ready to be “taped out”. This means that the full layout representation of the design is
written out in a standard format called GDSII – this file must contain ALL the physical data of
the design, not just the “abstract” data used during P & R.
UNIX structure as a design library database.
Reference libraries contain different views:
CEL: The full layout view
FRAM: The abstract view used for P&R, as well as DC Topographical
LM: Logic Model with Timing and Power info, used by layout tools
The timing and power information of the LM views is not used by DC Topographical – it gets its
timing (and if applicable, power) information from the target and link libraries.
The full layout (CEL) view is used after Placement and Routing (P & R) are completed, and the
design is ready to be “taped out”. This means that the full layout representation of the design is
written out in a standard format called GDSII – this file must contain ALL the physical data of
the design, not just the “abstract” data used during P & R.
Milkyway Reference and Design Libraries
Target and link libraries must still be specified for
logical, timing and power info
The reference libraries (standard cell and, if applicable, macro cell or IP libraries), along with the
technology file and TLU-plus file (if applicable) are all provided by the back-end vendor or library group.
The arrow from the reference libraries is dashed to indicate that the reference libraries are not
included in the design library – instead, the design library contains a “pointer” to the libraries.
Note: The recommended format for transferring design data between Design Compiler and
Physical Compiler or IC Compiler is ddc – not Milkyway.
For DC-to-Astro, output a Verilog netlist, along with the sdc constraints file.
Layout vs Abstract Views in Milkyway Library
A standard cell library also contains a corresponding
abstract view for each layout view
Abstract views contain only the minimal data needed
for Place & Route
The use of abstract views instead of cell views enables smaller, more efficient design databases to be built and manipulated by P&R tools.
The abstract views do not contain underlying device details (poly, diffusion, n-wells, contacts).
They contain only the following:
- Outline of the cell (The “placement” tool places each cell in available sites in the core of the
chip. All the placer needs to know is the size and shape (outline) of the cell.)
- Pin locations and layer (Pins are usually metal connections to the underlying poly or diffusion
areas of the devices. The “router” tool uses these pin locations to route metal wires or connections
to each cell)
- Metal blockages (Areas in a cell where metal of a certain layer can not be routed because that
layer is being used in the full layout of the cell, but does not show up as a pin in the abstract view.
The example layout above is too simple to require blockages. These are more commonly needed in macro cells)
The layout and abstract views of all standard cells are built by a Library group. These cells are
usually initially built in a standard format called GDSII and then converted into tool-specific
formats (e.g. Milkyway database format for use by Synopsys tools).
abstract view for each layout view
Abstract views contain only the minimal data needed
for Place & Route
The use of abstract views instead of cell views enables smaller, more efficient design databases to be built and manipulated by P&R tools.
The abstract views do not contain underlying device details (poly, diffusion, n-wells, contacts).
They contain only the following:
- Outline of the cell (The “placement” tool places each cell in available sites in the core of the
chip. All the placer needs to know is the size and shape (outline) of the cell.)
- Pin locations and layer (Pins are usually metal connections to the underlying poly or diffusion
areas of the devices. The “router” tool uses these pin locations to route metal wires or connections
to each cell)
- Metal blockages (Areas in a cell where metal of a certain layer can not be routed because that
layer is being used in the full layout of the cell, but does not show up as a pin in the abstract view.
The example layout above is too simple to require blockages. These are more commonly needed in macro cells)
The layout and abstract views of all standard cells are built by a Library group. These cells are
usually initially built in a standard format called GDSII and then converted into tool-specific
formats (e.g. Milkyway database format for use by Synopsys tools).
DFT再了解(三)
Structured DFT
1. Highly pushbutton—little intervention by designer
2. Each design is checked against a set of DRC rules
3. Violations are corrected by adding or modifying logic
The complexity of SoC designs is driving the need for structured DFT methodologies. A
structured methodology is one that globally resolves many on-chip testability issues. Such
methodologies are widely applicable to most designs without much customization. They are
automated. The tools do most of the DFT work with minimal intervention. Scan-based testing is
a typical structured methodology that will be emphasized in this course. Scan insertion, for
example, is relatively automated and independent of design function.
1. Highly pushbutton—little intervention by designer
2. Each design is checked against a set of DRC rules
3. Violations are corrected by adding or modifying logic
The complexity of SoC designs is driving the need for structured DFT methodologies. A
structured methodology is one that globally resolves many on-chip testability issues. Such
methodologies are widely applicable to most designs without much customization. They are
automated. The tools do most of the DFT work with minimal intervention. Scan-based testing is
a typical structured methodology that will be emphasized in this course. Scan insertion, for
example, is relatively automated and independent of design function.
2011年8月2日 星期二
乘加器
Subtraction by e becomes addition with its one’s complement plus 1.
Subtraction by f becomes addition with its one’s complement plus 1.
~e and ~f take priority to be summed since they should arrive earlier than the MULT_P outputs.
Two’s complement inversion of e and f generates two ‘1’s. Adding these two ‘1’s costs zero area
since the addition is accomplished by connecting two Cin inputs to Logic1.
Unused Cin inputs are connected to Logic0.
DFT再了解(二)
Full Scan Summary
Full Scan Advantages:
Needs only combinational ATPG (D-algorithm)
for testing all Stuck-At faults
Combinational ATPG gives shorter ATPG run times
Predictable and applies across most architectures
Gives highest test coverage of all the algorithms
Easiest to implement
Full Scan Limitations:
Adds nonfunctional pins to the package
Timing and density impact of scan-equivalent flops
Embedded memory, latches, and non-scan flip-flops,
require fast sequential ATPG (“almost-full scan”)
Full Scan Advantages:
Needs only combinational ATPG (D-algorithm)
for testing all Stuck-At faults
Combinational ATPG gives shorter ATPG run times
Predictable and applies across most architectures
Gives highest test coverage of all the algorithms
Easiest to implement
Full Scan Limitations:
Adds nonfunctional pins to the package
Timing and density impact of scan-equivalent flops
Embedded memory, latches, and non-scan flip-flops,
require fast sequential ATPG (“almost-full scan”)
2011年8月1日 星期一
Library 名詞表
- target_library : describes the cells you’re map to (.db file)
- link_library : describes cells you’ve instantiated, and any wire load or operating condition models you are using (.db file)
- symbol_library : contains symbols(.sdb file) for the GUI’s schematic viewer
- synthetic_library : contains soft macro(.sldb file) to implement math functions
- design_lib : Holds intermediate format descriptions of your HDL co
DFT再了解(一)
DFT Flow
set_dft_signal Specifies DFT signal types for DRC and DFT insertion
create_test_protocol Creates a test protocol based on user specification
dft_drc Checks the current design against test design rules
set_scan_configuration Specifies the scan chain design
set_scan_path Specifies a scan chain for the current design
preview_dft Previews, but doesn’t implement, the scan architecture
insert_dft Adds scan circuitry to the current design
set_dft_signal Specifies DFT signal types for DRC and DFT insertion
create_test_protocol Creates a test protocol based on user specification
dft_drc Checks the current design against test design rules
set_scan_configuration Specifies the scan chain design
set_scan_path Specifies a scan chain for the current design
preview_dft Previews, but doesn’t implement, the scan architecture
insert_dft Adds scan circuitry to the current design
2011年7月31日 星期日
Test coverage or fault coverage
Test Coverage is defined as the percentage of detected faults divided
by the ATPG detectable faults:
Target your test coverage and fault coverage
1. Fault Coverage at least : 95% for IP, 90% for ASIC
2.Test Coverage at least : 98 % for IP, 95% for ASIC
可依據每個design及project的特性調整coverage目標
by the ATPG detectable faults:
Target your test coverage and fault coverage
1. Fault Coverage at least : 95% for IP, 90% for ASIC
2.Test Coverage at least : 98 % for IP, 95% for ASIC
可依據每個design及project的特性調整coverage目標
Design rule constraints (DRCs)
Technology libraries contain vendor-specific design
rules for each cell, e.g. max_capacitance/transition
DRC (design rules checking)
rules for each cell, e.g. max_capacitance/transition
DRC (design rules checking)
Design Exchange Format (DEF) file
在 dc_shell-xg-t -topographical可以產生DEF檔給ICC吃
或是其它的floorplan工具也會產生DEF檔給ICC吃
如果是第一次設計不存在DEF文件
或是其它的floorplan工具也會產生DEF檔給ICC吃
如果是第一次設計不存在DEF文件
滑鼠的DPI和CPI參數有何區別
參考文件
http://registerboy.pixnet.net/blog/post/12306370
及
http://molex2009.blogspot.com/2009/07/dpicpi.html
CPI的全稱是counts-per-inch，意爲光電滑鼠在每英寸長度上的採樣精度。光學滑鼠的主流的解析度是400CPI，即每移動一英寸可反饋 400個不同的座標，也即定位的最小距離是1/400英寸（約0.0635毫米）。DPI是每平方英寸能識別/列印的點數，最早用於衡量掃描器和印表機的 指標參數。有人認爲使用CPI更能表現出滑鼠的採樣特點，但實際上二者並無太大的差別。現在生産廠家一般都只標注DPI的參數，DPI值越高，說明滑鼠的 精確度也就越好。
CPI與DPI皆是形容光學滑鼠分辨率的單位，而「DPI」原本是印刷方面的記量單位，而借過來給光學滑鼠分辨率的單位；而「CPI」是安捷倫（世界聞名 的光電鼠標引擎生產廠商）提出了自己的單位標準，即「CPI」。CPI的全稱是「count per inch」，直譯為「每英吋的測量次數」，由此可知這兩個單位並沒有優劣之分喔！
1、DPI(CPI)的意义
DPI(CPI)是一个表示精度的硬件指标。个人的理解，在光电鼠标中，这个量表示的是为了能被人观察到的屏幕上的变化，鼠标必须移动的最小的距离。这里 所说的能被人观察到的屏幕上的变化，可以是光标移动1个(或N个)像素，也可以是在FPS游戏里转身10度。这个变化可以由鼠标驱动或软件（游戏）的设定 来改变，但其中最基本、最细微的变化只能是光标移动1个像素。我们下面就讨论1个像素变化的情况。
而鼠标必须移动的最小的距离，是DPI的倒数。假设某鼠标是200DPI，那么这个鼠标A必须移动1/200英寸，屏幕上光标移动1个像素。而另一各 800DPI的鼠标B，只须移动1/800英寸，光标就能移动1个像素。这是第一层意义上的精度差别，就是鼠标对微小移动的响应能力。
当鼠标B移动了1/200英寸时，屏幕上光标可以移动4个像素。其表现出的结果就是鼠标B的光标移动速度是比鼠标A快4倍（这时候鼠标本身的移动速度是一样的）。
那么在同样的鼠标移动距离下，DPI值低的鼠标A能不能获得较高的光标的移动速度呢（注意，是光标的速度）？当然没问题，驱动里来个加速就行了。一次不是移动1个像素，而是4个像素，那么它就能和鼠标B的光标移动速度一样了。
但是新的问题又产生了，鼠标1本身快速移动的也许还看不出，当鼠标慢速移动时，就会发现鼠标在屏幕上的光标总是只能在4的倍数号的像素上停留，鼠标光标在跳动着移动。这是第二层意义上的精度差别，就是鼠标对屏幕像素的操纵能力。
所以高DPI鼠标，可以由小幅操作获得高响应，并同时保持高度的像素的操纵能力。
PI 原來是印刷方面的記量單位，表示每英吋上可以印刷的網點數量。後來常被應用於打印機、掃瞄儀等輸入、輸出設備，現在也經常用來形容光電鼠標的分辨率。 也就是說，DPI並不是形容光電鼠標分辨率的專有名詞，而是「借來」的單位。DPI的英文全稱是「dots per inch」，直譯為「每英吋像素」，可以用來表示光電鼠標在物理表面上每移動1英吋（約2.54厘米）時其傳感器所能接收到的坐標數量。比如，羅技MX 510光電鼠標的分辨率為800 DPI，也就是說當使用者將鼠標移動1英吋時，其光學傳感器就會接收到反饋回來的800個不同的坐標點，經過分析這800個不同坐標點的反饋，鼠標箭頭同 時會在屏幕上移動800個像素點。
對於光電鼠標的分辨率，安捷倫（世界聞名的光電鼠標引擎生產廠商）提出了自己的單位標準，即「CPI」。CPI的全稱是「count per inch」，直譯為「每英吋的測量次數」。因為光電鼠標的分辨率本身反映了一個動態的過程，單從單詞的直譯來說，「count」（測量）比「dots」 （像素）更加傳神。不過目前在光電鼠標的世界裡，「DPI」和「CPI」都可以成為形容光電鼠標分辨率的單位，性能方面沒有差異。
而對於光電鼠標的分辨率，不少朋友還有個誤解：分辨率越高，定位越準。而實際上，提高分辨率的根本目的就是減少使用者需要進行的物理位移。比如，某款光電 鼠標的分辨率是400 DPI，也就是說這款產品位移一英吋距離內可以測量400個像素，而測量每個像素就需要鼠標物理位移1/400英吋。那麼在1024×768的系統分辨率 下，如果將鼠標箭頭以直線方式由左上角的點移動到右上角的點，理論上就需要經過1024個像素，也就是說需要位移光電鼠標2.56（1024/400）英 吋。但如果這款光電鼠標的分辨率達到了800 DPI，顯然它只需要位移1.28英吋，鼠標則可以減少位移原距離的一半。由此可見，鼠標箭頭在系統裡位移同等距離時，光電鼠標的分辨率越高，所需要的物 理位移也就越短。在越高屏幕分辨率下工作，這種情況也就越明顯。因為屏幕像素越多，所需光標移動的距離也越長
http://registerboy.pixnet.net/blog/post/12306370
及
http://molex2009.blogspot.com/2009/07/dpicpi.html
CPI的全稱是counts-per-inch，意爲光電滑鼠在每英寸長度上的採樣精度。光學滑鼠的主流的解析度是400CPI，即每移動一英寸可反饋 400個不同的座標，也即定位的最小距離是1/400英寸（約0.0635毫米）。DPI是每平方英寸能識別/列印的點數，最早用於衡量掃描器和印表機的 指標參數。有人認爲使用CPI更能表現出滑鼠的採樣特點，但實際上二者並無太大的差別。現在生産廠家一般都只標注DPI的參數，DPI值越高，說明滑鼠的 精確度也就越好。
CPI與DPI皆是形容光學滑鼠分辨率的單位，而「DPI」原本是印刷方面的記量單位，而借過來給光學滑鼠分辨率的單位；而「CPI」是安捷倫（世界聞名 的光電鼠標引擎生產廠商）提出了自己的單位標準，即「CPI」。CPI的全稱是「count per inch」，直譯為「每英吋的測量次數」，由此可知這兩個單位並沒有優劣之分喔！
1、DPI(CPI)的意义
DPI(CPI)是一个表示精度的硬件指标。个人的理解，在光电鼠标中，这个量表示的是为了能被人观察到的屏幕上的变化，鼠标必须移动的最小的距离。这里 所说的能被人观察到的屏幕上的变化，可以是光标移动1个(或N个)像素，也可以是在FPS游戏里转身10度。这个变化可以由鼠标驱动或软件（游戏）的设定 来改变，但其中最基本、最细微的变化只能是光标移动1个像素。我们下面就讨论1个像素变化的情况。
而鼠标必须移动的最小的距离，是DPI的倒数。假设某鼠标是200DPI，那么这个鼠标A必须移动1/200英寸，屏幕上光标移动1个像素。而另一各 800DPI的鼠标B，只须移动1/800英寸，光标就能移动1个像素。这是第一层意义上的精度差别，就是鼠标对微小移动的响应能力。
当鼠标B移动了1/200英寸时，屏幕上光标可以移动4个像素。其表现出的结果就是鼠标B的光标移动速度是比鼠标A快4倍（这时候鼠标本身的移动速度是一样的）。
那么在同样的鼠标移动距离下，DPI值低的鼠标A能不能获得较高的光标的移动速度呢（注意，是光标的速度）？当然没问题，驱动里来个加速就行了。一次不是移动1个像素，而是4个像素，那么它就能和鼠标B的光标移动速度一样了。
但是新的问题又产生了，鼠标1本身快速移动的也许还看不出，当鼠标慢速移动时，就会发现鼠标在屏幕上的光标总是只能在4的倍数号的像素上停留，鼠标光标在跳动着移动。这是第二层意义上的精度差别，就是鼠标对屏幕像素的操纵能力。
所以高DPI鼠标，可以由小幅操作获得高响应，并同时保持高度的像素的操纵能力。
PI 原來是印刷方面的記量單位，表示每英吋上可以印刷的網點數量。後來常被應用於打印機、掃瞄儀等輸入、輸出設備，現在也經常用來形容光電鼠標的分辨率。 也就是說，DPI並不是形容光電鼠標分辨率的專有名詞，而是「借來」的單位。DPI的英文全稱是「dots per inch」，直譯為「每英吋像素」，可以用來表示光電鼠標在物理表面上每移動1英吋（約2.54厘米）時其傳感器所能接收到的坐標數量。比如，羅技MX 510光電鼠標的分辨率為800 DPI，也就是說當使用者將鼠標移動1英吋時，其光學傳感器就會接收到反饋回來的800個不同的坐標點，經過分析這800個不同坐標點的反饋，鼠標箭頭同 時會在屏幕上移動800個像素點。
對於光電鼠標的分辨率，安捷倫（世界聞名的光電鼠標引擎生產廠商）提出了自己的單位標準，即「CPI」。CPI的全稱是「count per inch」，直譯為「每英吋的測量次數」。因為光電鼠標的分辨率本身反映了一個動態的過程，單從單詞的直譯來說，「count」（測量）比「dots」 （像素）更加傳神。不過目前在光電鼠標的世界裡，「DPI」和「CPI」都可以成為形容光電鼠標分辨率的單位，性能方面沒有差異。
而對於光電鼠標的分辨率，不少朋友還有個誤解：分辨率越高，定位越準。而實際上，提高分辨率的根本目的就是減少使用者需要進行的物理位移。比如，某款光電 鼠標的分辨率是400 DPI，也就是說這款產品位移一英吋距離內可以測量400個像素，而測量每個像素就需要鼠標物理位移1/400英吋。那麼在1024×768的系統分辨率 下，如果將鼠標箭頭以直線方式由左上角的點移動到右上角的點，理論上就需要經過1024個像素，也就是說需要位移光電鼠標2.56（1024/400）英 吋。但如果這款光電鼠標的分辨率達到了800 DPI，顯然它只需要位移1.28英吋，鼠標則可以減少位移原距離的一半。由此可見，鼠標箭頭在系統裡位移同等距離時，光電鼠標的分辨率越高，所需要的物 理位移也就越短。在越高屏幕分辨率下工作，這種情況也就越明顯。因為屏幕像素越多，所需光標移動的距離也越長
Design Compiler再了解(三十三)
DC Ultra （Design Compiler的最高版本）
在Synopsys软件中完整的综合方案的核心是DC UltraTM，对所有设计而言它也是最好级别的综合平台。另外，DC Ultra采用后布局和优化布线技术，易于较快达到时序收敛。
DC Ultra综合引擎能提供DC Expert所有的功能，以及它的独特的优点。
能与DC Ultra共同工作的软件有路径综合、测试综合和功耗优化、静态时序和功耗分析，以及经验证的、高性能Design Ware库。这是经过验证的技术独特的集成，形成一个完整的综合解决方案，能在最短的时间里满足用户所有的设计挑战。
使用compile_ultra指令Scannable Equivalent Flip-Flop
The scan equivalent has a serial path from pin SIto SO
This path is enabled only during testing, by asserting SE
This path is enabled only during testing, by asserting SE
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