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2011年9月27日 星期二

PrimeTime再了解(二十七)

 Timing Exception Impact
特別時序指令的衝擊

1. 特別時序指令會花費許多的運算
Complexity of Timing Analysis ~=  
Latches + Flip--flops +   Timing exceptions + Clocks

例如一個指令如下
dc_shell-t> set_false_path -from U_CONTROL/reg*/CP -to U_DATA/reg*/D
如果reg是32bits 那就需要32x32 = 1024的運算

 2. 為了避免設定錯誤可以採用以下指令來看有設了那些特別時序指令
DC就用  report_timing_requirements -ignore

PT就用 report_exceptions

對於disable timing 就用 report_disable_timing

2011年9月26日 星期一

如何在PT及DC中加入新的指令

在DC或PT中如果要加上一個新的指令,如同report_timing,
可以用proc來做

加入一個加法指令
pt_shell> proc plus {a b} { return [expr $a + $b]}

 加入一個help說明
pt_shell> define_proc_attributes plus -info "Add two numbers" \
            -define_args { \
            {a "first addend" a string required} \
            {b "second addend" b string required} \
            {"-verbose" "issue a message" "" boolean optional}}


使用help的結果
pt_shell> help -verbose plus
Usage: plus    # Add two numbers
    [-verbose]         (issue a message)
    a                  (first addend)
    b                  (second addend)


使用指令的結果
pt_shell> plus 5 6
11


另一種方法Parsing Arguments Passed in to a Tcl Procedure

 加入一個argHandler的指令
proc argHandler {args} {
  parse_proc_arguments -args $args results
  foreach argname [array names results] {
    echo "  $argname = $results($argname)"
  }
}



添加指令變數
define_proc_attributes argHandler \
  -info "Arguments processor’ \
  -define_args {
  {{-Oos "oos help" AnOos one_of_string
      {required value_help {values {a b}}}}
   {-Int "int help" AnInt int optional}
   {-Float "float help" AFloat float optional}
{-Bool "bool help" "" boolean optional}
   {-String "string help" AString string optional}
   {-List "list help" AList list optional}}
   {-IDup "int dup" AIDup int {optional merge_duplicates}}}

使用help來看變數資訊
pt_shell> argHandler -help
Usage: argHandler    # argument processor
-Oos AnOos (oos help: Values: a, b)
[-Int AnInt]         (int help)
[-Float AFloat]      (float help)
[-Bool] (bool help)
[-String AString]    (string help)
[-List AList]        (list help)
[-IDup AIDup]        (Int dup)

錯誤使用後的反應
pt_shell> argHandler -Int z
Error: value 'z' for option '-Int' not of type 'integer'
(CMD-009)
Error: Required argument ‘-Oos’ was not found (CMD-007)


正確使用的反應
pt_shell> argHandler -Int 6 -Oos a -IDup 2 -IDup 3
  -Int = 6
  -Oos = a
  -IDup = 2 3

PrimeTime再了解(二十六)

Pre/Post Layout Clock

For post-CTS (Clock Tree Synthesis) static timing analysis set_propagated_clock 
forces the analyzer to calculate the ACTUAL clock tree skew, latency and transition times.

The post-CTS constraints therefore do not include ideal transition and network latency commands.

If the uncertainty number used during synthesis includes jitter and/or margin, these effects must still be included in the post-CTS analysis, along with the external source latency.

2011年9月25日 星期日

PrimeTime再了解(二十五)

Using Pulse Clocks



有三種方法來設定
1.  Use a pulse generator cell that has been characterized with pulse generator attributes in
the .lib description.

2. Use the create_generated_clock command to describe the pulse timing with respect
to the source clock.

3.  Use the set_clock_sense command to specify the sense of the generated pulses with
respect to the source clock.

方法一
The best method is to use a pulse generator cell that has been characterized in its .lib library
description. In that case, no additional action is necessary in PrimeTime to specify the pulse
clock characteristics. For information about specifying the pulse generator characteristics of
a library cell, see the Library Compiler documentation.


方法二
To specify the generated pulse clock CLKP as a generated clock:
pt_shell> create_generated_clock -name CLKP -source CLK  \
          -edges {1 1 3} [get_pins and2/z]

Specifying the generated clock as a pulse clock using repeated edge digits (rather than
specifying the pulse clock edge times) ensures correct checking of delays between the
source clock and the pulse clock.

In general, the position of the repeated digit determines whether an active-high or active-low
pulse is generated, and the edge number that is repeated determines the type of edge in the
master clock used to trigger the pulse:
•   -edges {1 1 3} -- rising edge of source triggers high pulse
•   -edges {2 2 4} -- falling edge of source triggers high pulse
•   -edges {1 3 3} -- rising edge of source triggers low pulse
•   -edges {2 4 4} -- falling edge of source triggers low pulse



方法三
Instead of using the create_generated_clock command to define a new clock, you can
use the set_clock_sense command to specify the sense of the existing clock:
pt_shell> set_clock_sense -pulse rise_triggered_high_pulse get+pins and2/z

In general, the clock sense of a pulse clock can be specified at a location in the design by
one of the following forms of syntax:
set_clock_sense -pulse rise_triggered_high_pulse object_list
set_clock_sense -pulse rise_triggered_low_pulse object_list
set_clock_sense -pulse fall_triggered_high_pulse object_list
set_clock_sense -pulse fall_triggered_low_pulse object_list


另一個set_clock_sense的例子
set_clock_sense -clock CLK -pulse rise_triggered_high_pulse [get_pins AND/Z]



另外對於propagated latency可以參考
The nominal width of the generated pulses is zero, whether you use a pulse generator cell
defined in the library, the create_generated_clock command, or the set_clock_sense
command. To determine the actual pulse width, PrimeTime considers the different rise and
fall latency values at the pulse generator output pin.
 (high pulse width) = (fall network latency) – (rise network latency)
 (low pulse width) = (rise network latency) – (fall network latency)

You can allow PrimeTime to calculate the propagated latency from the circuit, or you can use
the set_clock_latency command to specify the latency values (and therefore the pulse
width) explicitly. For example, to set an ideal pulse width to 0.5 for high pulses, for all
registers downstream from pin and2/z, and with an overall latency of 0.6, the commands
would be:
pt_shell> set_clock_latency -rise 0.6 and2/z
pt_shell> set_clock_latency -fall 1.1 and2/z




Constrain Minimum and Maximum Pulse Width in the Fanout of
Pulse Generator Cells

PrimeTime provides the ability to constrain the pulse clock network. The transitive fanout of
pulse generator is referred to as pulse clock network. The clock propagating through the
pulse generator in the pulse clock network is referred to as the pulse clock. However, if the
pulse generator has sequential arcs, its output is not a clock signal unless a generated clock
is defined at the output. Use the set_pulse_clock_min_width and
set_pulse_clock_max_width commands to constrain the pulse generator networks.

set_pulse_clock_min_width -transitive_fanout value object_list

set_pulse_clock_max_width -transitive_fanout value object_list

Regular Expressions in DC and PT

一些使用上的例子
 
 set gc [get_cells -regexp {i(1|2)_.*}]

 get_cells blk* -filter "ref_name =~ AN*"
get_cells -regexp {blk.*} -filter "ref_name =~ AN.*"

report_timing -from [list i1/* [get_pins -regexp $expr]]

get_cells -regexp i1.*

get_cells -regexp i1/i2.*/n1

get_cells -regexp -hierarchical ".*"  -filter {base_name == n1}

get_cells -regexp {.*U1.*}
This matches U1, U11, U1A, U1_23, plus ZU1, ZZU1, hello_U1, and so forth.

filter_collection -regexp [get_ports *] {full_name =~a\[[0-1]\]}

get_ports -regexp [list {a\[[0-1]\]}]
get_ports -regexp {{a\[[0-1]\]}}
get_ports -regexp {a\\[[0-1]\\]}
These two commands are essentially equivalent. Proper list forms require single backslash
quoting (\), just like string arguments. It is recommended that you use a properly formatted
list for a list argument, especially in this situation. However, when you pass a single string
into the “patterns” argument, double backslash quoting (\\) is required.

2011年9月24日 星期六

PrimeTime再了解(二十四)

Clock Sense


PrimeTime keeps track of inverters and buffers in clock trees. It recognizes the positive or
negative sense of the clock signal arriving at each register clock pin. No specific action is
necessary to tell PrimeTime the sense of a clock tree that has only buffers and inverters. In
this case, the clock signal arriving at the register clock pin is said to be “unate

對於 Non-Unate Clock Signals在PrimeTime該如何找出
To resolve this ambiguity for PrimeTime, you can specify the sense of a clock signal at a
point in the clock path using the set_clock_sense command. For example,
pt_shell> set_clock_sense -positive [get_pins xor1.z]

對於有多clock輸入時,可以指定clock
pt_shell> set_clock_sense -positive \
          -clock [get_clocks CLK] [get_pins mux1.z]

Clock Sense Examples


set_clock_sense -stop_propagation
You could use the -stop_propagation option to stop propagation of specified clocks in
the clock list from the specified pins or cell timing arcs in the object list. This is appropriate
in cases where the clock physically does not propagate past a certain pin as both clock
and clock as data propagation are stopped at the pin in any form.

set_clock_sense -logical_stop_propagation
You use the -logical_stop_propagation option to stop only the clock acting as a
clock, but not the clock acting as data propagation. You might want the clock to continue
to propagate forward, but in a way that PrimeTime does not analyze it as clock and only
treats the clock as data.
Note:  
The timing_arc object is supported only with the -stop_propagation option.


Physical Clock Stopping
In this case, TESTCLK never physically exists beyond UMUX2. To model this in PrimeTime, you should use the following command:
set_clock_sense -stop_propagation -clocks TESTCLK UMUX2/Z


It might be desirable to analyze the U3 through U5 buffers only as a data path. In this case, the clock could be logically stopped at the input of U3 by using the following command:

set_clock_sense -logical_stop_propagation -clocks CLK U3/A

2011年9月23日 星期五

PrimeTime再了解(二十三)

另一個範例關於多個clocks的設定方法
這些方法是從PrimeTime的文件抽出
但一樣適用於Desing Compile
 

Four Clocks and Two Selection Signals


設定方法1
To check all valid paths while avoiding invalid ones, you can declare false paths between the clocks:
pt_shell> set_false_path -from CK1 -to CK2
pt_shell> set_false_path -from CK2 -to CK1
pt_shell> set_false_path -from CK3 -to CK4
pt_shell> set_false_path -from CK4 -to CK3



設定方法2
Another way is to use case analysis and set logic values on S1 and S2 to check a particular case. For example,
pt_shell> set_case_analysis 0 [get_ports S1]
pt_shell> set_case_analysis 0 [get_ports S2] 


If you want to analyze all four cases using case analysis, four analysis runs are necessary,
with S1-S2 = 00, 01, 10, and 11. Still another way is to use the set_clock_groups and
set_active_clocks commands. For example,
pt_shell> set_clock_groups -logically_exclusive -name mux1 \
          -group {CK1} -group {CK2}
pt_shell> set_clock_groups -logically_exclusive -name mux2 \
          -group {CK3} -group {CK4}
pt_shell> set_active_clocks {CK1,CK2,CK3,CK4}

PrimeTime analyzes all valid paths from CK1 to CK3 and CK4, and from CK2 to CK3 and
CK4 (and in the opposite direction if there are any such paths), but not between CK1 and
CK2 or between CK3 and CK4.

If you only want to consider the case where S1-S2=00, you can do it easily by using a
different set_active_clocks command:
pt_shell> set_clock_groups -logically_exclusive -name mux1 \
          -group {CK1} -group {CK2}
pt_shell> set_clock_groups -logically_exclusive -name mux2 \
          -group {CK3} -group {CK4}
pt_shell> set_active_clocks {CK1,CK3}



 

Design Compiler再了解(五十四)

Using Multiple Clocks

有三種可能的多重clocks
1. Synchronous,
2. Asynchronous,
3. Exclusive Clocks

比較特別的是set_clock_groups的使用

If you specify more than two groups, each group is exclusive with respect to the other
specified groups. For example,
pt_shell> set_clock_groups -logically_exclusive \
          -group {CK1 CK2} -group {CK3 CK4} -group {CK5}

If you specify just one group, that group is exclusive with respect to all other clocks in the
design. For example,
pt_shell> set_clock_groups -logically_exclusive  -group {CK1 CK2}


You can optionally assign a name to a clock group declaration, which makes it easier to later
remove that particular declaration:
pt_shell> set_clock_groups -logically_exclusive -name EX1 \
          -group {CK1 CK2} -group {CK3 CK4}
Use the remove_clock_groups command to remove a clock grouping declaration:
pt_shell> remove_clock_groups -logically_exclusive -name EX1


To remove all exclusive clock grouping declarations made with the set_clock_groups
command:
pt_shell> remove_clock_groups -logically_exclusive -all

2011年9月22日 星期四

PrimeTime再了解(二十二)

一個範例關於多個clocks的設定方法
這些方法是從PrimeTime的文件抽出
但一樣適用於Desing Compile
 
Four Clocks and One Selection Signal
有不同的寫法



設定方法1
One way to prevent checking between unrelated clocks is to set a false path between the
clocks. For example,
pt_shell> set_false_path -from CK1 -to CK2
pt_shell> set_false_path -from CK2 -to CK1
pt_shell> set_false_path -from CK3 -to CK4
pt_shell> set_false_path -from CK4 -to CK3
pt_shell> set_false_path -from CK1 -to CK4
pt_shell> set_false_path -from CK4 -to CK1
pt_shell> set_false_path -from CK2 -to CK3
pt_shell> set_false_path -from CK3 -to CK2

In that case, PrimeTime tests all of the valid combinations of enabled clocks in a single run, while ignoring the invalid combinations. 


 

設定方法2
Another way is to use case analysis and set a logic value, either 0 or 1, on the SEL input, which checks the timing for a particular case of SEL=0 or SEL=1. 
For example,
pt_shell> set_case_analysis 0 [get_ports SEL]
With SEL=0, only CK1 and CK3 are active; CK2 and CK4 are ignored. If you want to analyze both cases, two analysis runs are necessary: one with SEL=0 and another with SEL=1. 

設定方法3 這個方法較適用於PT
Another method to accomplish the same effect is to use the set_disable_timing
command. For example, to disable checking of all paths leading from the CKP2 and CKP4 clock input pins of the design:
pt_shell> set_disable_timing [get_ports {CKP2 CKP4}]


設定方法4
Still another way is to specify which clocks can be active together at the same time and which clocks are currently active. For example,
pt_shell> set_clock_groups -logically_exclusive -name E1 \
            -group {CK1 CK3} -group {CK2 CK4}
pt_shell> set_active_clocks [all_clocks]

The set_clock_groups command defines groups of clocks that are exclusive with respect to each other. PrimeTime does not check paths that start from a clock in one group and end at a clock in another group. If you specify just one group, that group is considered exclusive with respect to all other clocks in the design.  


設定方法5
In the preceding example, the set_active_clocks command makes all four clocks active, so that PrimeTime analyzes all valid paths while avoiding the invalid clock combinations.
If you want to consider only the case where SEL=0, you can do it easily by using a different set_active_clocks command:
pt_shell> set_clock_groups -logically_exclusive -name E1 \
           -group {CK1 CK3} -group {CK2 CK4}
pt_shell> set_active_clocks {CK1,CK3}

Setting clocks CK1 and CK3 active means that CK2 and CK4 are inactive, which is just like using case analysis and setting SEL=0 or setting false paths between all combinations of clocks not using CK1 and CK3. 


2011年9月21日 星期三

PrimeTime再了解(二十一)

link 與  link_design

在PT中才有link_design

link   The  link command, a synonym for the link_design command, exists
              in PrimeTime for compatibility with Design Compiler.

同樣為了通用性的script
建議用link

2011年9月20日 星期二

PrimeTime再了解(二十)

 link_path  與  link_library的差異


在PT中才有link_path
而link_library在DC及PT中都有


在PT中使用man去查 
  link_path
           Specifies  a  list of libraries, design files, and library files
              used during linking.


  link_library
              This is a synonym for the link_path variable.


而在DC中使用man去查 
   link_library
              Specifies  the  list  of  design files and libraries used during
              linking.


所以link_library == link_path
但是為了Script的共用性
建議採用link_library




2011年9月19日 星期一

PrimeTime再了解(十九)

Timing closure efficiently

Grouping all of timing violations into several types:










set  ports_clock_root  [get_pins [all_fanout –flat –clock_tree –level 0]]
group_path  –name “Reg2Out”   –to [all_outputs]
group_path  –name “In2Reg”  \
–from [remove_from_collection [all_inputs] $ports_clock_root ]
group_path  –name  “Feedthrough”  \
-from [remove_from_collection [all_inputs] $ports_clock_root ]  \
-to [all_outputs]

把上面的這段script放在PT/DC中的report_timing之前

 Checking all violations
 report_constraint  -nosplit  -all_violators

report的順序如下























本區可參考網頁

http://kirenenko-tw.blogspot.com/2011/08/design-compiler_09.html

http://kirenenko-tw.blogspot.com/2011/08/design-compiler_5306.html

2011年9月18日 星期日

Design Compiler再了解(四十九)

最佳性能的最优化

資料由http://www.61ic.com/code/ 得來

方法三 展开关键路径的逻辑

由於不可能展开整个设计。在这里,你通过展开临界上的逻辑来提高性能。
    为展开临界路径上的逻辑,
1)用all_fanin命令来确定与临界路径相关的逻辑
dc_shell> all_fanin -to all_critical_pins() -only_cells
2)组合临界路径逻辑
dc_shell> group -design critical_block -cell_name cp1
3)描述临界路径逻辑的特色
dc_shell> characterize cp1
4)展开临界路径逻辑
dc_shell> current_design critical_block
dc_shell> set_flatten true
dc_shell> compile
dc_shell> set_flatten false
5)取消临界路径逻辑模块的组
dc_shell> current_design ..
dc_shell> ungroup -simple_names cp1

這樣只對需要優化的部份來展開
方便後續的其他動作

PrimeTime再了解(十八)

Specify false paths

設定false path的技巧
1.     Using Permutation and Combination [Mathematics] to set false paths
between all clock domains
2.     To hide the false paths which are relationship with each clock domain

以下是一個簡單例
## False paths from CLKC domain to the other domain
set_false_path –from [get_clock “CLKC” ]  -to [get_clock “CLKD”]
set_false_path –from [get_clock “CLKD” ]  -to [get_clock “CLKC”]
set_false_path –from [get_clock “CLKC” ]  -to [get_clock “gc_CLKD_1”]
set_false_path –from [get_clock “gc_CLKD_1” ]  -to [get_clock “CLKC”]
set_false_path –from [get_clock “CLKC” ]  -to [get_clock “gc_CLKD_2”]
set_false_path –from [get_clock “gc_CLKD_2” ]  -to [get_clock “CLKC”]

## False paths from CLKD domain to the other domain
## 紅色部分為可不設的重覆部份,因為前面已經會設定下面的部份
## set_false_path –from [get_clock “CLKD” ]  -to [get_clock “gc_CLKD_1”]
## set_false_path –from [get_clock “gc_CLKD_1” ]  -to [get_clock “CLKD”]
## set_false_path –from [get_clock “CLKD” ]  -to [get_clock “gc_CLKD_2”]
## set_false_path –from [get_clock “gc_CLKD_2” ]  -to [get_clock “CLKD”]

## False paths from gc_CLKD_1 domain to the other domain
set_false_path –from [get_clock “gc_CLKD_1” ]  -to [get_clock “gc_CLKD_2”]
set_false_path –from [get_clock “gc_CLKD_2” ]  -to [get_clock “gc_CLKD_1”]

另外
Setting false paths for test_mode/scan_enable signals

本區其他參考頁
http://kirenenko-tw.blogspot.com/2011/08/design-compiler_5306.html

http://kirenenko-tw.blogspot.com/2011/08/design-compiler_14.html



2011年9月17日 星期六

PrimeTime再了解(十七)

Specify ideal network

Design rule checks(DRCs) are disabled on clock networks (ideal
network) .

The latency and transition times of ideal clock are zero by default.









For synthesis(DC):
set_dont_touch_network  [all clocks]

For Layout tools
set_ideal_network [get_port “CLKA” ]
set_ideal_network [get_pin  “PLL/CKOUT”]
set_ideal_network [get_pin  “U3/Q”]




此處可參考
http://kirenenko-tw.blogspot.com/2011/08/design-compiler_5614.html

OpenRisc_CPU全定制芯片设计方法

參考
http://www.shangshuwu.cn/index.php/OpenRisc_CPU%E5%85%A8%E5%AE%9A%E5%88%B6%E8%8A%AF%E7%89%87%E8%AE%BE%E8%AE%A1%E6%96%B9%E6%B3%95

下次研究openrisc時有可參考的資料

2011年9月16日 星期五

2011年9月15日 星期四

Design Compiler再了解(四十七)

最佳性能的最优化

資料由http://www.61ic.com/code/ 得來

方法一 创建路径组 (group_path的使用)


默认时,Design Compiler根据控制终点的时钟组合路径(所有与时钟没有
关系的路径在一个默认的组中)。如果你的设计中有复杂的时钟、复杂的时序要求、或复杂的约束,你可以创建路径组,使得Design Compiler专注于设计中指定的关键路径。
    用命令group_path来创建路径组。命令group_path允许你:
1 控制设计的最优化
2.最优化接近临界的路径
3.  最优化所有路径

1)控制设计最优化
    你可以通过创建路径组和对其排序来控制最优化,这只影响最大延迟成本函数。默认情况下,Design Compiler只对每个组中的最差情况起作用。
    通过对每个组设置权(默认权是1.0),设置路径组的优先权。权可以是从0.0100.0





    比如,图显示了一个有多重路径到触发器FF1的设计:

    为指出从输入in3FF1的路径的优先权最高,采用下列命令:
dc_shell> group_path -name group3 \-from in3 -to FF1/D -weight 2.5


2)最优化接近临界的路径
    当你对一个路径组增加了临界范围,你改变了最大延迟成本函数。Design Compiler在临界范围内优化所有路径。
    指定一个临界范围会增加运行时间。为限制运行时间的增加,只在设计的最后实现阶段使用临界范围,并使用一个合理的临界范围值。一个最大临界范围值的方针就是时钟周期的10%。
    使用下列方法之一指定临界范围:
使用group_path命令的-critical_range选项
使用set_critical_range命令



   如下,图显示了一个带有三个输出ABC的设计:

    假设时钟周期为20ns,每一个输出的最大延迟为10ns,临界延迟如图所示。默认时,Design Compiler只优化最差情况(到输出A的路径)。为优化所有路径,设置临界延迟为3.0ns
dc_shell> create_clock -period 20 clk
dc_shell> set_critical_range 3.0 current_design
dc_shell> set_max_delay 10 {A B C}
dc_shell> group_path -name group1 -to {A B C}


你也可以用set_max_delayset_min_delay命令来约束穿越不同频率域的异步路径。
    比如:
dc_shell>set_max_delay 17.1 \-from find(clock, clk1) -to find(clock, clk2)
dc_shell> set_max_delay 23.5 \-from find(clock, clk2) -to find(clock, clk3)
dc_shell> set_max_delay 31.6 \-from find(clock, clk3) -to find(clock, clk1)


3)优化所有路径
    通过对设计的每一个终点创建一个路径组来对所有路径进行优化,但导致了更长的编译运行时间。利用下列脚本创建一个路径组:
endpoints = all_outputs() + all_registers(-data_pins)
foreach (endpt, endpoints) {
group_path -name endpt -to endpt
}

PrimeTime再了解(十五)

Clock Tree Balance

*** CTS ***
The priority of clock tree balance:
1. CTS for C and Fix
2. CTS for A
3. CTS for B





*** CTS ***
The priority of clock tree balance:
1. CTS for U3/Q
2. CTS for A








2011年9月14日 星期三

PrimeTime再了解(十四)

Create clock tree architecture


Consideration of clock tree balance priority

Dose clock tree exist overlap?

Clock tree architecture
•   Create_clock or Create_generated_clock ?
•   Exist  Multiplexer、 Divider cell or  asynchronous circuit with clock domain?
•   Clock Period
•   Flip-Flop number

Specify Sync pin or Ignore pin