关键字“ifdef”用来判断一个变量是否已经定义。格式为：
`ifdef VARIABLE-NAME'
例1：
bar =
foo = $(bar)
ifdef foo
frobozz = yes
else
frobozz = no
endif
例2：
foo =
ifdef foo
frobozz = yes
else
frobozz = no
endif
例1中的结果是：“frobozz = yes”；而例2的结果是：“frobozz = no”。其原因就是在例1中，变量“foo”的定义是“foo = $(bar)”。虽然变量“bar”的值为空，但是“ifdef”判断的结果是真。因此当我们需要判断一个变量的值是否为空的情况时，需要使用“ifeq”（或者“ifneq”）而不是“ifdef”。可参考前两个小节的内容。
virtual function void lock_model()
Lock a model and build the address map.
Recursively lock an entire register model and build the address maps to enable the uvm_reg_map::get_reg_by_offset() and uvm_reg_map::get_mem_by_offset() methods.
Once locked, no further structural changes, such as adding registers or memories, can be made.
It is not possible to unlock a model.鎖住了就不能再設定了
function void set_hdl_path_root ( string path, string kind = "RTL" )
Specify a root HDL path
Set the specified path as the absolute HDL path to the block instance for the specified design abstraction. This absolute root path is preppended to all hierarchical paths under this block. The HDL path of any ancestor block is ignored. This method overrides any incremental path for the same design abstraction specified using add_hdl_path.
指向對映這個uvm_reg_block的實體設計的path
這個path必須自行指定，例如
string hdl_root = "tb_top.dut";
regmodel.set_hdl_path_root(hdl_root);
| virtual function void add_reg ( | uvm_reg | rg, | |||
| uvm_reg_addr_t | offset, // 這個對映的uvm_reg的起始位置 | ||||
| string | rights | = | "RW", | ||
| bit | unmapped | = | 0, | ||
| uvm_reg_frontdoor | frontdoor | = | null | ) |
| virtual function void add_mem ( | uvm_mem | mem, | ||||
| uvm_reg_addr_t |
| |||||
| string | rights | = | "RW", | |||
| bit | unmapped | = | 0, | |||
| uvm_reg_frontdoor | frontdoor | = | null | ) |
Block abstraction base class
A block represents a design hierarchy. It can contain registers, register files, memories and sub-blocks.
A block has one or more address maps, each corresponding to a physical interface on the block.
在裡面包含了uvm_reg_field, uvm_mem, uvm_reg...
一個簡單的uvm_reg_block範例
class dut_regmodel extends uvm_reg_block;
rand dut_ID ID; // uvm_reg
rand dut_DATA DATA;// uvm_reg
rand dut_SOCKET SOCKET[256]; // uvm_reg, array type
rand dut_RAM RAM; // uvm_mem
function new(string name = "slave");
super.new(name,UVM_NO_COVERAGE);
endfunction
virtual function void build();
// create
ID = dut_ID::type_id::create("ID");
DATA = dut_DATA::type_id::create("DATA");
foreach (SOCKET[i])
SOCKET[i] = dut_SOCKET::type_id::create($sformatf("SOCKET[%0d]",i));
RAM = dut_RAM::type_id::create("DMA_RAM");
// configure
ID.configure(this,null,"ID");
ID.build();
DATA.configure(this,null,"DATA");
DATA.build();
foreach (SOCKET[i]) begin
SOCKET[i].configure(this,null,$sformatf("SOCKET[%0d]",i));
SOCKET[i].build();
end
RAM.configure(this,"DMA");
// define default map, 因為uvm_reg_block內部有一個預設的uvm_reg_map叫default_map
//對每一個uvm_reg_block 都必須將map設定好，可使用內定function default_map來創建map
default_map = create_map("default_map", 'h0, 4, UVM_LITTLE_ENDIAN, 1);
default_map.add_reg(ID, 'h0, "RW");
default_map.add_reg(DATA, 'h24, "RW");
foreach (SOCKET[i])
default_map.add_reg(SOCKET[i], 'h1000 + 16 * i, "RW");
default_map.add_mem(RAM, 'h2000, "RW");
endfunction
`uvm_object_utils(dut_regmodel)
endclass : dut_regmodel
uvm_reg_map的create_map，要放在uvm_reg_block用
| virtual function uvm_reg_map create_map( | string | name, | |||
| uvm_reg_addr_t | base_addr, | ||||
| int | unsigned | n_bytes,// 一次讀寫的bytes數 | |||
| uvm_endianness_e | endian, | ||||
| bit | byte_addressing | = | ) |
| function new ( | string | name, | | |||
| longint | unsigned | size, // total memory size | | |||
| int | unsigned | n_bits, // 每一個位址所含的bits數 | | |||
| string | access | = | "RW", | |||
| int | has_coverage | = | UVM_NO_COVERAGE | ) |
| 1 | IEEE 1364-2001 | Verilog Hardware Description Language |
| 2 | IEEE 1800-2009 | SystemVerilog–Unified Hardware Design, Specification, and Verification Language |
| 3 | IEEE 1076-2002 | VHDL Language Reference Manual |
| 4 | IEEE 1076-1993 | VHDL Language Reference Manual |
| 5 | IEEE 1499-1998 | Interface for Hardware Description Models of Electronic Components |
| 6 | IEEE 1364-1995 | Hardware Description Language Based on the Verilog® Hardware Description Language |
| 7 | IEEE 1800-2005 | SystemVerilog: Unified Hardware Design, Specification and Verification Language |
| 8 | IEEE 1076.2-1996 | VHDL Mathematical Packages |
| 9 | IEEE 1076.1-1999 | VHDL Analog and Mixed-Signal Extensions |
| 10 | IEEE 1685-2009 | IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows |
| 11 | IEEE 1850-2005 | Property Specification Language (PSL) |
| 12 | IEEE 1076c-2007 | VHDL Language Reference Manual – Procedural Language Application Interface |
| 13 | IEEE 1164-1993 | Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) |
| 14 | IEEE 1850-2010 | Property Specification Language (PSL) |
| 15 | IEEE 1076.6-2004 | VHDL Register Transfer Level (RTL) Synthesis |
| 16 | IEEE 1801-2009 | Design and Verification of Low Power Integrated Circuits |
| 17 | IEEE 1481-2009 | Integrated Circuit (IC) Open Library Architecture (OLA) |
| 18 | IEEE 1076.4-1995 | VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification |
| 19 | IEEE/IEC 61691-5-2004 | IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
| 20 | IEEE 1647-2008 | Functional Verification Language e |
| 21 | IEEE 1076.1.1-2011 | VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support |
| 22 | IEEE/IEC 61691-7-2009 | Behavioural languages – Part 7: SystemC Language Reference Manual |
| 23 | IEEE 1076-1987 | VHDL Language Reference Manual |
| 24 | IEEE 1076.1.1-2004 | VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support |
| 25 | IEEE 1076.3-1997 | VHDL Synthesis Packages |
| 26 | IEEE/IEC 61523-3-2004 | IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process |
| 27 | IEEE 1076/INT-1991 | Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual |
| 28 | IEEE/IEC 62531-2007 | IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL) |
| 29 | IEEE 1076.6-1999 | VHDL Register Transfer Level Synthesis |
| 30 | IEEE 1647-2006 | Functional Verification Language “e” |
| 31 | IEEE/IEC 61691-6-2009 | Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions |
| 32 | IEEE 1666-2005 | SystemC® Language Reference Manual |
| 33 | IEEE/IEC 61691-1-1-2004 | IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual |
| 34 | IEEE 1364-2005 | Verilog Hardware Description Language |
| 35 | IEEE/IEC 61691-4-2004 | IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog® Hardware Description Language |
| 36 | IEEE 1076.4-2000 | VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification |
| uvm_report_info | |
| uvm_report_warning | |
| uvm_report_error | |
| uvm_report_fatal |
2-state data value with `UVM_REG_DATA_WIDTH bits
4-state data value with `UVM_REG_DATA_WIDTH bits
2-state address value with `UVM_REG_ADDR_WIDTH bits
4-state address value with `UVM_REG_ADDR_WIDTH bits
2-state byte_enable value with `UVM_REG_BYTENABLE_WIDTH bits
Coverage model value set with `UVM_REG_CVR_WIDTH bits.
Symbolic values for individual coverage models are defined by the uvm_coverage_model_e type.
The following bits in the set are assigned as follows
| 0-7 | UVM pre-defined coverage models |
| 8-15 | Coverage models defined by EDA vendors, implemented in a register model generator. |
| 16-23 | User-defined coverage models |
| 24.. | Reserved |
Slice of an HDL path
Struct that specifies the HDL variable that corresponds to all or a portion of a register.
| path | Path to the HDL variable. |
| . | Offset of the LSB in the register that this variable implements |
| size | Number of bits (toward the MSB) that this variable implements |
If the HDL variable implements all of the register, offset and size are specified as -1. For example:
r1.add_hdl_path('{ '{"r1", -1, -1} });| function new ( | string | name | = | "", | ||
| int | unsigned | n_bits, | ||||
| int | has_coverage | ) |
| function void configure( | uvm_reg | parent, | ||
| int | unsigned | size, | ||
| int | unsigned | lsb_pos, // 在此uvm_reg下起始的packet bits位置 | ||
| string | access, | |||
| bit | volatile, | |||
| uvm_reg_data_t | reset, | |||
| bit | has_reset, | |||
| bit | is_rand, | |||
| bit | individually_accessible | ) |
