The standard cell portion of the chip design except macro blocks is implemented
with an internal scan.
The interfaces for the internal scan implementation should be reserved advance.
The signals reserved include scan_clock, test_reset, scan_enable, scan_in,
scan_out, and scan_mode (`1' in scan & ATPG mode).
The signals scan_enable, scan_in_0, and scan_in_n are connected between Mode
Generation Module and Core. They are left floating and wait for DFT implementation.
The scan output signals scan_out_0, and scan_out_n are tied to 0 in the boundary of
Debug Module and wait for DFT implementation.
沒有留言:
張貼留言