DFT再了解(十二)

Architecture of Mode Generation Module












There are three main blocks included, a mode generator, an I/O control
signal generator, and a signal multiplexer.

Mode Generator
The mode generator takes the operation mode switch pin “Opmode_in” and the
mode selection pin “mode_sel” to generate a bunch of test-enable signals.
When any one of the test-enable signals is enabled. the chip is set to test mode.

I/O control signal generator
The I/O control signal generator controls the share of function pins to deliver
data-in and control signals.
These shared pins can be input pins or in-out pins.
If the in-out pins are shared and the test mode is enabled, the I/O control signal
generator issues I/O control signals to place the shared pin in the input status.

Signal multiplexer
The signal multiplexer creates the paths for DFT designs and the shared pins.
If a DFT designs is placed in the test mode, the test signals and data pins of
DFT designs are connected to the primary inputs of shared pins.
Therefore, the DFT designs can be tested via the primary inputs.