Design Compiler再了解(十八)

Reading Designs with analyze & elaborate

set search_path “$search_path rtl unmppd mppd”
analyze –format verilog {A.v TOP.v}
Compiling source file .../risc_design/rtl/A.v
Compiling source file .../risc_design/rtl/TOP.v
elaborate MY_TOP
...
Current design is now ‘MY_TOP’
Reading ddc file ‘.../risc_design/unmppd/MY_B.ddc’.
Reading ddc file ‘.../risc_design/mppd/MY_C.ddc’.

取代了 current_design or link!

analyze
- Reads source code files (Verilog or VHDL RTL)
- Checks syntax and issues errors/warnings
- Converts both Verilog and VHDL files into intermediate binary format files, placed in CWD
- Can use define_design_libto redirect the files/directories to a sub-directory


elaborate
- Reads the intermediate .pvl files and builds the ‘GTECH’ design in DC memory (unmapped
ddc format)
- Sets the current design to the specified design
- Links and auto-loads the specified design
- Allows specification of parameter values: elaborate MY_TOP -parameters “N=8, M=3”.
- Caution: If available, a .ddc file will be loaded and will over-write an RTL source code
design that was explicitly analyzed, if the .ddc file is found in the search_path directories.

當TOP如下時
module MY_TOP (A, B, C, ... );
parameter A_WIDTH 2;
parameter B_WIDTH 4; ...
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B; ...
MY_A U1 (.A1 (A), ...
MY_B U2 (.B1 (B), ...

elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16”
可以在此設定變數值

elaborate是設定變數值的唯一的方法

不良RTL設計的探討

一個不良的設計






1. Design Compiler must preserve block pin definitions
Logic optimization – e.g. merging of combinational logic -
does not occur across block boundaries

2. Path from REG A to REG C may be larger and slower
than necessary Poorly partitioned!

不良的設計會導致合成上問題，應該盡可能的避免。
當然coding style也會產生其它的問題，
此處可查閱相關的RTL coding style
synopsys的內部文件有相關的說明


較好的設計








1. Related combinational logic is grouped into one block:
No hierarchy separates combinational functions
A, B, and C

2. Combinational optimization techniques can now be
fully exploited Faster and smaller combo logic!

3. However, no sequential optimization possible at REG C



另一種較差的設計













在Design的TOP總是會有一些Glue Logic來連結次module
但是如果全部都是自己作的就可以將上面的NAND放到C module下
而如果是整合的人，因為設計不是你，所以不得已還是會用到Glue Logic

Synopsys有提供一些注意事項
1. No combinational optimization between glue logic and combo logic C

2. If the top-level blocks A, B and C are large and will be synthesized
separately (middle-up compile strategy), an additional compile is
needed at top-level


最後
(Quality of Results – QoR) relies on good coding style
(Quality of Source – QOS).

Linux的指令 tee

參考網址
http://ccd9527.blogspot.com/2009/05/linux-tee.html
http://linux.vbird.org/linux_basic/0320bash/0320bash.php#tee

whoami | tee whoami.file
同時把結果存到檔案中，又可以顯示在螢幕上哩

如果要把要顯示在螢幕上的再分析一次哩，那請用
whoami | tee whoami.file | 分析指令

tee導向的部分只有standard output的部分，沒有導向standard input與standard error的部分

Design Compiler再了解(十七)

Saving the ddc Design After compile給ICC使用

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
link
check_design
write –format ddc –hier –output unmapped/MY_TOP.ddc
source TOP.con
check_timing
compile –boundary –scan –map high
change_names –rule verilog -hier
write –format verilog –hier –output mapped/MY_TOP_ntl.v 1
write –format ddc –hier –output mapped/MY_TOP.ddc

The ddc format stores the design netlist, constraints and
attributes. This is an efficient format to either re-read the
design into DC or to read the design into ICC.

Design Compiler再了解(十六)

在DC中使用ddc file的好處與方法

好處
The read command takes RTL code and builds a ‘GTECH’ design
in DC memory – i.e. translates into unmapped ddc format

1. RTL-to-ddc translation of large designs may take some time
2. May need to re-read the un-compiled design in the future
3. read_ddc is faster

產生ddc file的方法
There are two methods for saving hierarchical designs. The first method is the more common
approach. In both examples the current design is MY_TOP

1. One file containing the entire design hierarchy:
write –format ddc –hier –out unmapped/MY_TOP.ddc

2. Individual files containing parts of the design hierarchy:
write –format ddc –out MY_TOP.ddc (writes the current_designby default)
write –format ddc MY_A –out MY_A.ddc
write –format ddc MY_B –out MY_B.ddc

此處的ddc是在compile之前

Design Compiler再了解(十五)

check_design

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
link
check_design ##
source TOP.con ...

The check_design command, just like the link command, returns a ‘1’ or ‘0’ value to indicate if the
action was completed without, or with any serious problems, respectively.

可以把上面script改成如下

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
if {[link] ==0} {
echo “Linking Error”
exit; # Exits DC if a serious linking problem is encountered
}
if {[check_design] ==0} {
echo “Check Design Error”
exit; # Exits DC if a check-design error is encountered
} ; # Script continues to execute if NO problems encountered
source TOP.con
compile –boundary –scan –map high

Design Compiler再了解(十四)

Example Hierarchical Design
包含.v, .db , .ddc

DECODE and ENCODE are compiled sub-designs saved as ddc format files decode.ddc and
ENCODE.ddc, respectively.

讀取ddc file如下
set search_path “$search_path ../JOE/mapped”

然後在link前
read_ddc {decode.ddc ENCODE.ddc}
要注意大小寫


使用db file如下
set link_library “* $target_library IP.db”

















參考的script

set search_path “$search_path ../JOE/mapped”
set link_library “* $target_library IP.db”
read_verilog {A.v B.v TOP.v}
read_ddc decode.ddc
current_design MY_TOP
link

Design Compiler再了解(十三)

Startup File Name – Three File Locations

一起動DC，synopsys_dc.setup就會被自動執行
Default及首先被使用 …/admin/setup/.synopsys_dc.setup
其它的若存在則會覆蓋前面的執行變數














These files are automatically executed,
in the order shown, upon startup of DC.

Design Compiler再了解(十二)

search_path的設定參考








CWD是我們目前執行的目錄

set search_path “$search_path mapped rtl \
libs cons”

Design Compiler再了解(十一)

.synopsys_dc.setup的範例

set search_path “$search_path mapped rtl libs cons”
set target_library 65nm.db
set link_library “* $target_library”
set symbol_library 65nm.sdb
history keep 200
alias h history
alias rc “report_constraint -all_violators”

Design Compiler再了解(十)

Helpful UNIX-like DC_Shell commands

Find the location and/or names of files
dc_shell-xg-t> pwd; cd; ls

Show the history of commands entered:
dc_shell-xg-t> history

Repeat last command:
dc_shell-xg-t> !!

Execute command no. 7 from the history list:
dc_shell-xg-t> !7

Execute the last report command:
dc_shell-xg-t> !rep

Execute any UNIX command:
dc_shell-xg-t> sh

Get any UNIX variable value:
dc_shell-xg-t> get_unix_variable

For example, use the following to determine if you are in a Sun or Linux environment:
dc_shell-xg-t> get_unix_variable ARCH may return “linux” or “sparcOS5”

Design Compiler再了解(九)

XG mode 與 ddc file的使用

XG mode uses optimized memory management
techniques that increase the tool’s capacity and can
reduce runtime

In XG mode, all synthesis tools use the tool
command language (Tcl)

XG mode does not support the dcsh command
language

For DC versions 2004-12 and 2005.09 it is necessary to explicitly include “-xg” to invoke DC in
XG mode: dc_shell-xg-t, or design_vision-xg. (XG mode not available prior to
2004.12)

DB versus XG are two different memory management modes. DB mode is the default mode for
synthesis tool version W-2005.09 and earlier. In general, dc_shell behaves the same in DB mode and XG mode, but XG mode can provide you with reduced memory consumption and runtime.

Use the new binary .ddc format to save design netlists
Use in the same way as the old .db format

dc_shell-xg-t> read_ddc MYDES.ddc
dc_shell-xg-t> write –format ddc –hierarchy –output MYDES.ddc

Convert old .db to .ddc for maximum benefit
Use of the .db format for storing designs is still possible, but
highly discouraged - results in significant memory overhead

dc_shell-xg-t> read_db MYDES.db; # Reverts DC to ‘DB mode’
dc_shell-xg-t> write –format ddc –hierarchy -output MYDES.ddc

Formality supports the .ddc format beginning with the V-2004.06 release.
Physical Compiler XG mode, PrimeTime, and PrimePower support the .ddc format beginning with the W-2004.12 release

Design Compiler再了解(八)

特別注意事項

Do not set an external input delay on the clock port !

dc_shell-t> create_clock -period 10 [get_ports CLK]
dc_shell-t> set_input_delay 3 -clock CLK \
[remove_from _collection [all_inputs] [get_ports CLK]]




Do not forget the clock controlling a port external delay!  If needed create a virtual clock.

dc_shell-t> create_clock -p eriod 10 -name VIRT_CLK
dc_shell-t> set_input_delay 3 -clock VIRT_CLK [get_ports A]


Do not use max/min delays to constraint combo logic!

dc_shell-t> create_clock -period 12 -name CLK_VIRT
dc_shell-t> set_input_delay 0 -clock CLK_VIRT [get_ports A]
dc_shell-t> set_output_delay 0 -clock CLK_VIRT [get_ports B]


Do not forget to fully specify the constraints!
By default (without -fall/-rise or -max/-min), commands are symmetric 

dc_shell-t> set_input_delay -fall 3 -clock CLK [get_ports A]
dc_shell-t> set_input_delay -rise 2 -clock CLK [get_ports A]

Design Compiler再了解(七)

Network latency models the average ‘internal’ delay from the
create_clock port or pin to the register clock pins

Source latency models the delay from the actual clock origin to
the create_clock port or pin:













有寫source是在pin/port之前
set_clock_latency -source –max 3 [get_clocks CLK]

否則就是pin/port之後
set_clock_latency –max 1 [get_clocks CLK] ;# pre layout

一個很不錯的數位設計的paper網站

對數位IC設計深入技術有興趣的人可參考這個網站
http://www.sunburst-design.com/papers/

ddc file format

ddc consists of the same information as a .db file.

ddc is, by default, an internal DC format, which can also explicitly be written out.
Note: db is the old DC format which has been replaced by ddc (in XG mode)

ddc is a synopsys encrypted form of your design which can be read by the tools such as Design compiler, IC compiler and prime time.

It consists of the netlist(list of components and nets) information of your design along with the constraints which you have specified for implementing the design.

The .ddc format is backward compatible but not forward compatible.

This format contains back-annotated net delays and constraints. Subsequent topographical mode sessions restore virtual layout data.

The .ddc format is recommended for subsequent topographical mode optimizations and verification. Because when you read the RTL code the unmapped design can be stored in a .ddc format so that when you reread the design the tool can run faster when compared to a verilog or vhdl format.

Design Compiler再了解(六)

Uncertainty

Uncertainty models the maximum delay difference between
the clock network branches, known as clock skew,
but can also include clock jitter and margin effects:







The default clock uncertainty is zero.
Uncertainty can also be defined between clock domains with as follows:
set_clock_uncertainty –setup TU –from clk1–to clk2















By default, the command “set_clock_uncertainty” assigns the same value to the setup
and the hold uncertainty, unless either the –setup or the –hold switch are used.

This allows the design to be synthesized with extra “clock period margin” for setup timing, which does not apply to hold timing.