Library corner

以0.18來看

Slow Corner (max)
–  Temperature = 125 .C
–  Voltage = 1.8 - 1.8 * 10% = 1.62 V
–  Cell Delay In This Library for Setup Timing Check


Typical Corner
–  Temperature = 25 .C
–  Voltage = 1.8 V


Fast Corner (min)–  Temperature = -40 OC
–  Voltage = 1.8 + 1.8 * 10% = 1.98 V
–  Cell Delay In This Library for Hold Timing Check

一個關於 ESL + SOC +Embedded World的網站

http://funningboy.blogspot.com/

DFT再了解(二十七)

DFT specification commands 共有四種

 set_* Creates the specification
 report_* Reports the specification
 reset_* Restores settings back to default
 remove_* Removes the specification

例如
set_dft_signal » report_dft_signal » remove_dft_signal

ATPG再了解(九)

Empty Boxes Versus Black Boxes

使用下面指令
set build -reset_boxes # clears black & empty box list
set build -empty_box BUS_SWITCH
set build -black RAM32x8 -empty IRQ_CORE


An “empty box” is similar to a black box with the exception that its output pins are floating.
These can be used for an embedded memory with tristate-able outputs.

Specify an Empty Box module only if its outputs are actually at Z state during test. The empty box can be helpful if multiple modules are connected to a bus, but the module outputs are all at Z state.

Using black boxes in this case would result in bus contention.

Two additional ‘box’ models are supported To make TetraMAX treat a module as a library cell, use the –design_box option:

TetraMAX will then add faults to just the ports of this module, but not inside

To maintain the port connections of a level of hierarchy, use the –portfault_box option:
May be used in SoCBIST flow where scan ports of a module need to be maintained in design

ATPG再了解(八)

Duplicate Module Definitions

By default, if a module
definition already exists in
the internal list and a second
module with the same name
is read this will replace the
first definition:

An N5 violation (severity
warning) will be issued

To prevent module redefinition of any kind, set the N5 rule to
severity error:
TEST-T> set rule n5 error

DFT再了解(二十六)

Create Test Protocol

Specify Scan In
Define scan in signal that you want to be connected during insert_dft
















Specify Scan Out

Define scan out signal that you want to be connected during insert_dft

















Specify Scan Chains

ATPG再了解(七)

Saving ATPG Patterns
















There are currently three ASIC vendor specific formats supported by TetraMAX. FTDL is the
Fujitsu format, TDL91 is the Texas Instruments format, TSTL2 is the Toshiba format. Other ASIC vendors rely on using WGL. Each vendor will have different requirements regarding WGL. Please consult your ASIC vendor in order to use the proper setup for pattern output.

Note there is the command “set wgl” to adjust the WGL pattern output.

DFT再了解(二十五)

Create Test Protocol

Specify Scan Enable

Define scan in signal that you want to be connected during insert_dft
















For ICG Insertion Purpose
Define scan enable signal that are already connected in scan-ready netlist
















For ICG Insertion Purpose after 2008.09 release
Define scan enable signal that that you want to be connected during insert_dft

關於Cache的網站

http://blog.csdn.net/chinacodec/article/details/3408560
http://blog.csdn.net/chinacodec/article/details/3408591
http://blog.csdn.net/chinacodec/article/details/3408660
http://blog.csdn.net/chinacodec/article/details/3408673
http://blog.csdn.net/chinacodec/article/details/3408682
http://blog.csdn.net/chinacodec/article/details/3408686

http://en.wikipedia.org/wiki/CPU_cache


http://en.wikipedia.org/wiki/Cache_coherency

ATPG再了解(六)

Review Summary Report

在完成ATPG之後
可用
report_summaries
來看coverage

以下是執行範例
run_atpg -auto

# Step 7: Review Test Coverage

report_summaries
analyze_faults -class au

執行結果例
TEST-T> report_summaries
report_summaries
Uncollapsed Stuck Fault Summary Report
-----------------------------------------------
fault class code #faults
------------------------------ ---- ---------
Detected DT 143143
Possibly detected PT 768
Undetectable UD 1053
ATPG untestable AU 836
Not detected ND 2214
-----------------------------------------------
total faults 148014
test coverage 97.66%
-----------------------------------------------
Pattern Summary Report
-----------------------------------------------
#internal patterns 318
#basic_scan patterns 251
#fast_sequential patterns 67
-----------------------------------------------

DFT再了解(二十四)

Create Test Protocol

D. Specify Scan Mode
Define scan mode signal that are already connected in RTL
















For AutoFix Purpose
Define scan mode signal that you want to be connected during insert_dft














For Internal Pins Flow
Define scan mode signal that are already connected in RTL















For Internal Pins and AutoFix Purpose
Define scan mode signal that you want to be connected during insert_dft

DFT再了解(二十三)

Create Test Protocol

在讀進了RTL及LIB後
## Specify technology library
set target_library my_tech.db
set link_library my_tesh.db
## read design
read_verillog rtl_files.v
current_design top_level_design
link

就可以開始進行 Create Test Protocol

The Test Protocol describes how the design operates in scan mode

The Test Protocol needs to be created prior to running DFT operations
such as DRC checks, previewing the scan architecture, and inserting
the scan architecture

Steps for Creating a Test Protocol :
1. Define test signals : clocks, resets, test mode, constants, etc.
set_dft_signal -view {spec | existing} -type {signal_type} ….

2. Create / Read the test protocol using
create_test_protocol or read_test_protocol


按步驟來

A.Default Timing Configuration
Variables that affect the timing in the Test Protocol
Create_test_protocol also needs event order on the tester













B. Specify Scan Clock














再定義一次如果要用在insert_dft for AutoFix Purpose
Define clock signals that you want to be connected during insert_dft
















C. Specify Reset















再定義一次如果要用在insert_dft for AutoFix Purpose

ATPG再了解(五)

Prepare for ATPG and Run ATPG

在吃進SPF後
執行
run atpg -auto

Always start with –auto. It provides the best starting point
and tradeoff between coverage and pattern count in the
current and future releases.

Auto Option:
This option runs ATPG in incremental mode, going from basic through sequential modes.
It automatically includes high pattern-compaction options, reducing test-program length.

下面是參考的scripts
set_messages -log lab1.log -replace

# Step 1: Reading libraries

read_net ../libs/libs_tmax.v.gz
read_net ../libs/rams.v
set_build -black_box PLL
set_build -black_box CLKMUL

# Step 2: Read design

read_netlist ../design_data/orca_final.v

# Step 3: Build ATPG Model

run_build_model

# Step 4: Perform Scan Design Rules Check

run_drc ../design_data/orca_final.spf

# Step 5: Prepare for ATPG

add_faults -all
set_atpg -capture 4

# Step 6: Run ATPG engine(s)

run_atpg -auto

整個指令細項
run_atpg
[-auto_compression]
[basic_scan_only | fast_sequential_only | full_sequential_only]
[-distributed]
[-ndetects ]
[-nodisturb_clock_grouping]
[-observe_file ]
[–only_chain_test]
[-random]
[-rerun_for_timing_exceptions]
[-resolve_differences]

以下是說明
How the Automatic Mode of Run ATPG Operates

The -auto_compression option of the run_atpg command can be helpful to assist with the optimal generation of compact sets of ATPG patterns. It is designed to automatically select the best settings and algorithms to provide reasonably good results. This page explains the sequence of steps used when run_atpg -auto_compression is selected.

Auto compression uses two algorithms: multiple fault sensitization and secondary test generation. Multiple fault sensitization, only enabled through -auto_compress, is a fast test generation algorithm that results in lower pattern count. Secondary fault test generation is good at detection, but slower than multiple fault sensitization.

Please Note that there is a restriction that the pattern source must be set to internal, the default.

1. User Pre-sets: Before beginning, you should use the set_atpg command to pre-select the ATPG abort limit, ATPG verbose mode, and possibly the ATPG merge effort. You may also wish to create a non-default fault population, or you can use defaults for any or all of these settings.

Once your ATPG setup is done, you initiate auto mode with the run_atpg -auto_compression command.
2. Fault List: If there is no existing fault population, then an add_faults -all is performed. If a fault population exists, it is left undisturbed and used for the remainder of steps.
必要時執行

3. Pattern Generation: A run_atpg pass is performed with pattern storage enabled and dynamic merge on. Merge effort is set to high, unless you have preset merge to some other value. The ATPG abort limit and capture cycle depth is whatever you have pre-selected. Verbose mode will also be whatever you have pre-selected. If capture cycles have been set to a number greater than 1, Fast-Sequential ATPG may be performed after Basic-Scan ATPG. Also, if -full_seq_atpg has been set on, Full-Sequential ATPG may be performed after Basic-Scan or Fast-Sequential.
4. Reports: After completion of ATPG, a report of fault summaries, test coverage, and pattern counts is produced. In addition, the total CPU time is reported.
5. Restoration: All settings are restored to their original values.

Note that multiple fault sensitization is only available if you use the -auto_compression option.

DFT再了解(二十二)

set_dft_signal的使用方法

The set_dft_signal command is used to define
signals that are required for the test protocol

set_dft_signal -view
-type
-port
-active_state <0 | 1>
-hookup_pin
-timing

DFT Compiler uses views with the set_dft_signal
command to control how DFT signal are used by
dft_drc and insert_dft

 1. -view spec : DFT signals that DFT Compiler should use
during insert_dft (default) ONLY for insert_dft

2. -view existing_dft : DFT signals which must be
understood for the design to pass dft_drc
ONLY for dft_drc


The –view options can be abbreviated. For example:
“-view spec” -> “-view s” -> “-v s”
“-view existing_dft” -> “-view exist” -> “-v e”

-timing option is used to define
timing and waveform for a clock or reset signal


Specify a Clock
set test_default_period 100
set_dft_signal –view existing_dft \
-type ScanClock \
-port clock –timing [list 45 55]










Specify a Reset set_dft_signal –view existing_dft \
-type Reset \
-port resetn –active_state 0

Specify a Constant set_dft_signal –view existing_dft \
-type Constant \
-port atpgmode –active_state 1

Since the connection is made to bypass reset using atpgmode, we define this port as
“–view existing_dft –type constant” NOT “–type TestMode”.

Specify a Scan In
set_dft_signal \
-view spec
-type ScanDataIn \
-port test_si \
-hookup_pin U1/Z

Specify a Scan Out
set_dft_signal \
-view spec
-type ScanDataOut \
-port test_so \
-hookup_pin U2/A

Specify a Scan Enable
Scan enable used for both dft_drc and insert_dft
set_dft_signal –view exist –active 1 \
-type ScanEnable -port test_se \
-hookup_pin U3/Z

set_dft_signal –view spec –active 1 \
-type ScanEnable -port test_se \
-hookup_pin U3/Z













1. Since the scan enable is already routed to the clock gating cells and we need dft_drc to understand that it will be set to a 1 during shift, we need to declare the test_se port as
–view exist.

If It was only declared as –view spec, then dft_drcwill flag all the flops that are driven by
these clock gating cells as violated. You will end up with uncontrollable clock violations D1/D9.

ATPG再了解(四)

Perform Design Rule Checks

在執行完 run_build_model
之後執行
run_drc DUT.spf
將DUT.spf吃進來

run drc in TetraMAX is nearly identical to dft_drc in DFT Compiler

以下是參考scripts
# Step 1: Reading libraries

read_net ../libs/libs_tmax.v.gz
read_net ../libs/rams.v
set_build -black_box PLL
set_build -black_box CLKMUL

# Step 2: Read design

read_netlist ../design_data/orca_final.v

# Step 3: Build ATPG Model

run_build_model

# Step 4: Perform Scan Design Rules Check

run_drc ../design_data/orca_final.spf

In DRC (design rules checking) mode you specify all information needed by the tool to configure
the design for test. The test procedure file (STIL = Standard Test Interface Language) is read in. If DRC was successful, you get into Test mode.

TetraMAX的環境設定

因為TetraMAX會去參考SYNOPSYS及SYNOPSYS_TMAX這兩個變數
因此要將它們設成TetraMAX的安裝路徑

以下是bash的設法
export SYNOPSYS=/mnt/eda/Synopsys/tx2009.06
export SYNOPSYS_TMAX=/mnt/eda/Synopsys/tx2009.06

TMAX_HOME=/mnt/eda/Synopsys/tx2009.06
#alias tmax 'TMAX_HOME/bin/tmax \!*'
export PATH=$PATH:$TMAX_HOME/bin:./

附註
For backward compatibility, you can still set $SYNOPSYS_TMAX. If $SYNOPSYS_TMAX is
set, it will override $SYNOPSYS.

The following conditions and rules apply to specifying the location for installing TetraMAX:

1. SYNOPSYS is set and SYNOPSYS_TMAX is not set. This is the preferred and recommended condition.

2. SYNOPSYS_TMAX is set and SYNOPSYS is not set. The tool will set SYNOPSYS using the value of SYNOPSYS_TMAX and continue.

3.  Both SYNOPSYS and SYNOPSYS_TMAX are set. SYNOPSYS_TMAX will take precedence and SYNOPSYS is set to match before invoking the kernel.

4. Both SYNOPSYS and SYNOPSYS_TMAX are set, and are of different values, then a warning message is generated similar to the following:

WARNING:
WARNING:  $SYNOPSYS and $SYNOPSYS_TMAX are set differently,
using $SYNOPSYS_TMAX
WARNING:      SYNOPSYS_TMAX = /mount/groucho/joeuser/tmax
WARNING:      SYNOPSYS      = /mount/harpo/production/synopsys
WARNING:
WARNING:  Use of SYNOPSYS_TMAX is outdated and support for
this will be removed
WARNING:  in a future release.  Please use SYNOPSYS instead.
WARNING:

DFT再了解(二十一)

Scan Chains的估算

The number of scan chains varies depending on the register count and
available pins resource.

The integration engineer should estimate the maximum register count
that will be implemented in further applications.

It is recommended to stitch (1,000 ~ 2000) registers in a scan chain for
a reasonable testing time.

Try to build as balanced a set of top-level scan chains as possible

Unbalanced chains lead to :

Wasted test application time on tester.

Wasted pattern memory on tester.

Wasted $$