DFT Plan issues
How many test signals does DFT need?
Which port is scan enable (dedicate)?
Which port is scan test mode (dedicate)?
Which port is scan clock (dedicate)?
Have enough design resource to complete DFT?
If existing Bi-directional (in-out) ports? How to control them ?
What kind of coding style does DFT implementation need?
Asynchronous or synchronous design style?
How many gate clock in your design?
How many latch cells in your design?
How many macro cells in your design?
What kind of design architecture does DFT integration need ?
Mode Generation and Debug architecture
Clock architecture
Set/Reset architecture
How many scan chains? Scan chains balanceable?
What is your test coverage or fault coverage target ?
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