Design Compiler再了解(三十二)

Boundary Optimization

compile –boundary –scan -map_effort high

在我們使用Boundary Optimization時會因為需要Timing的修正
所以會用FF的QN-pin去消除一個INV-Cell，
這時在作pre/post-sim時會因為test-pattern需要這個INV的pin來作monitor
遇到這個情形，就會發生模擬不正確的。
要解決這個問題就要指令set_boundary_optimization來修正

當我們有必要保留某些cell/instance時
可用
set_boundary_optimization U2 false

當然反向來看
set_boundary_optimization {U0 U2} true

Design Compiler再了解(三十一)

Specifying Wire Loads

首先要知道在library中有哪些wire load model可用
使用 report_lib fast ; ##使用0.18的fast library

得到
Wire Loading Model:

Name : tsmc18_wl10
Location : fast
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 66.667
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 66.67

Name : tsmc18_wl20
Location : fast
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 133.334
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 133.33

Name : tsmc18_wl30
Location : fast
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 200.001
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 200.00

Name : tsmc18_wl40
Location : fast
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 266.668
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 266.67

Name : tsmc18_wl50
Location : fast
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 333.335
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 333.33

Name : ForQA
Location : fast
Resistance : 0
Capacitance : 1
Area : 1
Slope : 1
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 0.00
10 0.00


然後我們選擇最後一個
使用 get_attribute fast ForQA

DFT 名詞解釋

SA1 Fault:
Due to a defect, input pin A
of U0acts as if stuck high,
independent of input signal

SA0 Fault:
Due to defect, output pin Y
of U1acts as if stuck low,
independent of the inputs

Fault Model:
A logical model representing the effects of a physical defect

Stuck-At Fault (SAF)

Single Stuck-At Fault (SSAF)

defective parts per million (DPPM)

The testable flip-flop has two modes:
Normal mode—where the ASIC is operating as it was functionally designed to operate.
Test mode—where the ASIC is undergoing manufacturing test.

Level-sensitive scan design (LSSD) is a latch-based replacement for single latches,
master-slave latches, or flip-flops. It requires three separate clock lines to be routed.

A Full Scan design is one in which all of the flip-flops in the design have been scan replaced and will be included in the scan-chain.
Note: No memories, latches.

there are three additional ports now: SI (Scan In), SO (Scan Out), and SE (Scan Enable).
The command to stitch up the scan-chains is: insert_dft.

AjarDSP - open source DSP

官網在http://code.google.com/p/ajardsp/

AjarDSP (ajar as in slightly open) is an open source implementation of a synthesizable 16-bit dual-mac VLIW DSP with accompanying tools.

Design Compiler再了解(三十)

如何設定一個正確的operation condition

Use list_libto find the library name
列出我們有吃入的library 名稱
dc_shell> list_lib
Logical Libraries:
-------------------------------------------------------------------------
Library File Path
------- ---- ----
fast fast.db /mnt/eda/library/TSMC/0.18/synopsys
slow slow.db /mnt/eda/library/TSMC/0.18/synopsys
gtech gtech.db /mnt/eda/Synopsys/dc2009.06/libraries/syn
standard.sldb standard.sldb /mnt/eda/Synopsys/dc2009.06/libraries/syn
dw_foundation.sldb dw_foundation.sldb /mnt/eda/Synopsys/dc2009.06/libraries/syn


Use report_lib fast 去列出library fast 內部的資料
....
....
Operating Conditions:


Operating Condition Name : fast
Library : fast
Process : 1.00
Temperature : 0.00
Voltage : 1.98
Interconnect Model : balanced_tree
....
....

如果是90nm的library中
report_lib nom_90nm

Operating Conditions:
Name Library Process Temp Volt
----------------------------------------------------
lib default 1.00 25.00 1.00
WCCOM nom_90nm 1.50 70.00 0.95
WCMIL nom_90nm 1.50 125.00 0.90
BCCOM nom_90nm 0.60 0.00 1.05
BCMIL nom_90nm 0.60 -55.00 1.10


所以90nm 的operation condition可以設成
set_operating_conditions -max “WCCOM”


另外因為0.18 已經根據operation condition分成fast與slow這兩個選項了
而180nm fast library的operation condition則只有fast這個選項
所以不用設定
NO NEED TO SET AN OPERATING CONDITION!!

在90nm中
如果我們只要用default的設定
就用
get_attribute my_lib default_operating_conditions

其中my_lib = the name of your technology library (not the library file name).

Design Compiler再了解(二十九)

Input Transition的設定方法

最基本的方式
set_input_transition 0.12 [get_ports A]


另一種已知或猜測input端的cell，然後以這個Cell的输出驅動為設計的輸入能力
假設前端的cell為OR3B或FD1
set_driving_cell –lib_cell OR3B [get_ports A]
or
set_driving_cell –lib_cell FD1 –pin Qn [get_ports A]

Intel x87 FPU的使用基础

參考網頁
http://blog.csdn.net/zenny_chen/article/details/6186820

Intel x87 FPU专门用于执行标量浮点计算，可以对单精度浮点（32位）、双精度浮点（64位）以及扩展双精度浮点（80位）进行计算，并顺从IEEE754标准。

x87 FPU可以工作在32位兼容模式下以及64位模式下，在这两种下，FPU的数据寄存器的个数都一样，只有8个。对x87 FPU的数据寄存器的访问方式与一般的寄存器有所不同，它是栈式访问。你通过FLD指令把外部数据搬到x87 FPU的数据寄存器中时，那么x87 FPU会根据所搬数据的长度（32位、64位、80位）将输入数据分别对待为单精度浮点、双精度浮点和扩展双精度浮点方式，然后统一转为双精度扩展模式放 到数据栈顶。因此x87 FPU的数据寄存器长度为80位，并且后续的浮点计算都是基于扩展双精度进行的。

在栈顶的数据寄存器索引为0，那么它下面一个就是1， 然后是2， 以此类推，到栈底则为7。数据输出到存储器时使用FST或FSTP指令，前者仅仅是根据目标存储器的长度（32位、64位、80位）将扩展双精度类型分别 转为单精度、双精度、扩展双精度类型，然后输出到指定的存储器位置中。对于FSTP指令，除了将数据搬到外部外，还会执行推出堆栈的操作。另外，FLD和 FST以及FSTP还能搬移FPU内部寄存器的数据，FLD的作用是将指定的FPU数据寄存器位置的数据搬移到栈顶寄存器中，而FST则是将栈顶寄存器的 数据搬移到指定的FPU数据寄存器的位置。

这边要注意的是，由于80位（10个字节）并不是32位（4个字节）的整数倍，因此数据加载或存储双精度扩展浮点往往是用96位（12个字节）为单 位进行，所以“tbyte”所指的就是“twelve bytes”，呵呵呵。这里可以列一下Intel汇编格式的字节、字宽指定修饰词——byte（字节，8位），word（字，16位），dword（双 字，32位），qword（四字，64位），tbyte（十二字节，96位），mmword（64位，但只能用于MMX指令集 中），xmmword（128位，用于SSE指令集），ymmword（256位，用于最新的AVX指令集）。

Design Compiler再了解(二十八)

Automatic Partitioning

當然如果懶的用手動來設定Partitioning區塊
就使用Automatic Partitioning的指定吧

compile_ultra; # auto-ungrouping enabled by default

compile -auto_ungroup area|delay

##ungroup the entire hierarchy
compile –ungroup_all

Design Compiler再了解(二十七)

group and ungroup

我們可以手動來作partition，來加強某些部分的最佳化合成
這樣的好處在於，如果整合的人無法修改design，
但又需要對某些地方作最佳化，
可以將特殊的幾個module圈起來(group)，
再用分散(ungroup)來對這個地方作flatten，進而最佳化，
手動最佳化可以確認優化處是所要的地方，
避免不必要的地方因最佳化而導致錯誤。










.



group -design_name NEW_DES \
-cell_name U23 {U2 U3}

















ungroup –start_level 2 U23

















如果需要將所有的cell flatten 可用以下指令
ungroup –all –flatten

What is a Standard Cell Library?

Standard cell libraries describe the layout of basic combinational and sequential logic gates like:
• inverters
• buffers
• ands
• ors
• nands
• nors
• muxes
• latches
• flip-flops

Standard cell libraries are generally called “reference” libraries. These reference libraries are
technology specific and are usually created and provided by an external ASIC vendor or internal
library group.

In addition to standard cell libraries, reference libraries also contain pad cell libraries for signal IO and power/ground pad cells, as well as macro cell or IP libraries for reusable IP like RAMs,
ROMs, and other predesigned, standard, complex blocks.

加法器與合成

CSA is an adder architecture used to calculate intermediate partial sum values.
CSA architecture saves the entire carry vector to avoid carry-propagation delay overhead.
A tree structure of CSAs is typically used to reduce the number of input vectors from N down to 2.
A conventional adder (ripple, cla, clf) is required at the bottom of the CSA tree to add the final 2
vectors and produce the final sum.


















如果有特殊的加法器需求，就只好用DesignWare
列表如下
- Serial-prefix (rpl)
- Flexible carry-select
- Kogge-Stone parallel-prefix
- Mux-based prefix circuit
- Use of inverting full-adder cells
- Sklansky parallel-prefix

Design Compiler再了解(二十六)

Time Budgeting

Synopsys的建議是在INPUT/OUPUT PORT上
內部的design為40%
外部的環境為60%

例子如下

create_clock -period 10 [get_ports CLK]
set_input_delay -max 6 -clock CLK [all_inputs]
remove_input_delay [get_ports CLK]
set_output_delay -max 6 -clock CLK [all_outputs]

10ns的clock
對外面的預算delay是6ns，但clock可以不計

還有外部的電容負載可以用估計會有幾個fanout再用cell去加總

set_load [expr [load_of ssc_core_slow/and2a0/A] * 5] \
[all_outputs];
此例為估計fanout會有5個and2ao的A port

Design Compiler再了解(二十五)

What is a virtual clock

1. A clock that is not connected to any port or pin within
the current design

2. Serves as a reference for input or output delays

3. Creates a clock object with a user-specified name
within Design Compiler’s memory

範例
create_clock -name VCLK -period 2
要有name命名，後面不需要設定pin或port

Design Compiler再了解(二十四)

特殊指令

remove_input_delay
remove_output_delay

可以移除一些 pin/port的constraint，例如 clk/reset

remove_input_delay [get_ports Clk]

Design Compiler再了解(二十三)

redirect的好處

在synthesis的過程中
我們如果要將一些中間的資料輸出來作檢查
可以使用這個指令來儲存資料
如下面例子

redirect –tee –file precompile.rpt {link}
redirect –append –tee –file precompile.rpt {check_design}
redirect –append –tee –file precompile.rpt {source –echo -ver TOP.con}
redirect –append –tee –file precompile.rpt {report_port –verbose}
redirect –append –tee –file precompile.rpt {report_clock}
redirect –append –tee –file precompile.rpt {report_clock –skew}
redirect –append –tee –file precompile.rpt {check_timing}

Scheme to PDEF

Synopsys provides a binary utility, scheme2pdef to convert the Astro floorplan into a PDEF file for Physical Compiler. The scheme2pdef utility performs the following tasks:

1. scheme2pdef generates a scheme file dump.scm, that contains the procedure dumpEverything;

2. dumpEverything dumps the floorplan information into files in a specified directory (argument to dumpEverything);

3. scheme2pdef converts the PDEF file from the data dumped by dumpEverything, as below command.

scheme2pdef -tech ./library/ tsmc13fsg_6lm.tf -sitemap ./ sitemap -dumpdir dump -output fp.pdef

And the following data/files are the requirements to convert Astro floorplan scheme into PDEF

- Astro design database

- Astro technology file

- site map file

The difficulty is preparing the sitemap file. The sitemap file defines the unit title size for Physical Compiler, its width and height can be found in Synopsys physical library (.plib) or milkyway technology file (.tf).

Design Compiler再了解(二十二)

收集相關聯的net/pin/port/cell...的用法

1. 使用排除方式
remove_from_collection的範例用法

set all_inputs_except_clk \
[remove_from_collection [all_inputs] \
[get_ports *CLK*]]

把所有的input port中的clk相關的都排除掉

2. 另外也可以用filter的功能，收集想要的部份

Use the filter_collection command to get only
objects you are interested in:
The -filter option is a nice short-cut:
Relational operators are:
==, !=, >, <, >=, <=, =~, !~

filter_collection [get_cells *] “ref_name =~ AN*”
filter_collection [get_cells *] “is_mapped != true”
get_cells * -filter “dont_touch == true”
set fastclks [get_clocks * -filter “period < 10”]

get_cells -hier -filter “is_unmapped != true”
get_cells -hier -filter “is_hierarchical == true”

3. 另外的迴圈式的收集方法
foreach_in_collection cell [get_cells -hier * -filter \
“is_hierarchical == true”] {
echo “Instance [get_object_name $cell] is hierarchical”
}

Design Compiler再了解(二十一)

在port/pin上的负載電容與速度相對衝突

1. set_max_transition 3 [all_outputs]

2. set_load -pin_load 2.5 [get_ports *]

3. set_max_capacitance 0.6 [current_design]

第三項與第二項就直接衝突
然後二三項對第一項的速度會造成影響

所以設定時要根據library與外在環境來作最佳設定

如果是Chip，則因為有大驅動的PAD所以影響較小

另一個使用範例
set all_in_ex_clk [remove_from_collection \
[all_inputs] [get_ports Clk]]

# Assume a weak driving buffer on the inputs
set_driving_cell -lib_cell inv1a1 $all_in_ex_clk

# Limit the input load 1
set MAX_INPUT_LOAD [expr \
[load_of ssc_core_slow/and2a1/A] * 10]

set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clk

# Model the max possible load on the outputs, assuming
# outputs will only be tied to 3 subsequent blocks 1
set_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]


要設定這些變數
請參考cell timing model，要看lib檔才可以
或者在DC或PT使用 report_lib -timing typ_db  NAND2X1

以下是參考設定值
#=======================================
# Specify Max/Min Transition
#=======================================
# Default by Library Setting
set_max_transition  4.5  ${CurrentDesign}
set_min_transition   0.0  ${CurrentDesign}
#=======================================
# Specify Max/Min Capacitance
#=======================================
# Default by Library Setting
set_max_capacitance  0.3 ${CurrentDesign}  ;;Total ( Pins + Wire) capacitance
set_min_capacitance   0.0 ${CurrentDesign}
#=======================================
# Specify Max Fanout
#=======================================
set_max_fanout  50 ${CurrentDesign}
set_max_fanout  1 [all_inputs]

針對max_fanout有下列說明可參考

在最优化时，Design Compiler试图满足每一个驱动管脚的扇出负载限制。如果一个管脚违反了扇出负载限制，Design Compiler会尽力改正这个问题（比如通过改变这个元件的驱动能力）。

    

 工艺库可能对整个库指定默认的扇出约束，或对库描述的一个单独的单元里特定的管脚指定扇出约束。为确定你的工艺库是否为扇出计算而模拟，你可以对单元的输入管脚搜索fanout_load属性：

dc_shell> get_attribute find(pin, my_lib/*/*) fanout_load

     

用set_max_fanout命令对设计或输入管脚设置比工艺库里指定的更为保守的扇出约束（用set_fanout_load命令对输出端口设置预期的扇出负载值）。set_max_fanout命令通过对指定对象设置max_fanout属性对设计中的所有线或指定的输入端口设置最大扇出负载。比如，要对设计adder中的所有线设置max_fanout为16，输入：

dc_shell> set_max_fanout 16 find(design, adder)

    

 如果你用set_max_fanout命令和存在库的max_fanout属性，Design Compiler会尽力满足更小的扇出限制。

     

用remove_attribute命令来取消set_max_fanout命令，比如，输入：

dc_shell> remove_attribute find(design,adder) max_fanout

default.svf在DC flow中的作用

在DC的flow中
這個檔案 records the "changes" that boundary optimization,
register repositioning and ungrouping make to the design.

This file is readable by Formality, Synopsys’ formal verification or equivalency checking tool

因此這個檔案只能在synopsys的Tools中使用
如果我們要改變名字
set_svf file_name
把指令放在DC flow的前面



如果我們要用LEC
那就必須改變輸出檔
使用
set_vsdc
就變成了ASCII Mode檔
這樣就可以給別的Tool吃了

Design Compiler再了解(二十)

如何確認DesignWare可用
及相關的License

dc_shell> get_license DesignWare
1
dc_shell> list_licenses

Licenses in use:
Design-Compiler
DesignWare
1

Design Compiler再了解(十九)

Reading Designs with acs_read_hdl

相當於analyze + elaborate，但是不需要列出rtl檔，
只需要設定TOP name
就會自動從search_path去讀取所需檔案

set search_path “$search_path rtl unmppd mppd”
acs_read_hdl MY_TOP
Compiling source file .../risc_design/rtl/A.v
Compiling source file .../risc_design/rtl/TOP.v
...
Current design is now ‘MY_TOP’
Reading ddc file ‘.../risc_design/unmppd/MY_B.ddc’.
Reading ddc file ‘.../risc_design/mppd/MY_C.ddc’.

If a design has been read in from Verilog or VHDL source code, and that design also exists as a .ddc file in the search_path list,
the .ddc design replaces the source code design (same behavior as elaborate).

如果要使用輸入變數，可用下面的方法
acs_read_hdl –no_elaborate TOP
elaborate TOP –param “X=3 Y=5”