2011年9月24日 星期六

PrimeTime再了解(二十四)

Clock Sense


PrimeTime keeps track of inverters and buffers in clock trees. It recognizes the positive or
negative sense of the clock signal arriving at each register clock pin. No specific action is
necessary to tell PrimeTime the sense of a clock tree that has only buffers and inverters. In
this case, the clock signal arriving at the register clock pin is said to be “unate

對於 Non-Unate Clock Signals在PrimeTime該如何找出
To resolve this ambiguity for PrimeTime, you can specify the sense of a clock signal at a
point in the clock path using the set_clock_sense command. For example,
pt_shell> set_clock_sense -positive [get_pins xor1.z]

對於有多clock輸入時,可以指定clock
pt_shell> set_clock_sense -positive \
          -clock [get_clocks CLK] [get_pins mux1.z]

Clock Sense Examples


set_clock_sense -stop_propagation
You could use the -stop_propagation option to stop propagation of specified clocks in
the clock list from the specified pins or cell timing arcs in the object list. This is appropriate
in cases where the clock physically does not propagate past a certain pin as both clock
and clock as data propagation are stopped at the pin in any form.

set_clock_sense -logical_stop_propagation
You use the -logical_stop_propagation option to stop only the clock acting as a
clock, but not the clock acting as data propagation. You might want the clock to continue
to propagate forward, but in a way that PrimeTime does not analyze it as clock and only
treats the clock as data.
Note:  
The timing_arc object is supported only with the -stop_propagation option.


Physical Clock Stopping
In this case, TESTCLK never physically exists beyond UMUX2. To model this in PrimeTime, you should use the following command:
set_clock_sense -stop_propagation -clocks TESTCLK UMUX2/Z


It might be desirable to analyze the U3 through U5 buffers only as a data path. In this case, the clock could be logically stopped at the input of U3 by using the following command:

set_clock_sense -logical_stop_propagation -clocks CLK U3/A

一個clock switch glitch free的參考圖

Glitch protection for unrelated clock source







雖然是針對Glitch protection for unrelated clock sources
但也是可以用在related clock sources,只是設計稍大一點(多兩個latch)

2011年9月23日 星期五

PrimeTime再了解(二十三)

另一個範例關於多個clocks的設定方法
這些方法是從PrimeTime的文件抽出
但一樣適用於Desing Compile
 

Four Clocks and Two Selection Signals


設定方法1
To check all valid paths while avoiding invalid ones, you can declare false paths between the clocks:
pt_shell> set_false_path -from CK1 -to CK2
pt_shell> set_false_path -from CK2 -to CK1
pt_shell> set_false_path -from CK3 -to CK4
pt_shell> set_false_path -from CK4 -to CK3



設定方法2
Another way is to use case analysis and set logic values on S1 and S2 to check a particular case. For example,
pt_shell> set_case_analysis 0 [get_ports S1]
pt_shell> set_case_analysis 0 [get_ports S2] 


If you want to analyze all four cases using case analysis, four analysis runs are necessary,
with S1-S2 = 00, 01, 10, and 11. Still another way is to use the set_clock_groups and
set_active_clocks commands. For example,
pt_shell> set_clock_groups -logically_exclusive -name mux1 \
          -group {CK1} -group {CK2}
pt_shell> set_clock_groups -logically_exclusive -name mux2 \
          -group {CK3} -group {CK4}
pt_shell> set_active_clocks {CK1,CK2,CK3,CK4}

PrimeTime analyzes all valid paths from CK1 to CK3 and CK4, and from CK2 to CK3 and
CK4 (and in the opposite direction if there are any such paths), but not between CK1 and
CK2 or between CK3 and CK4.

If you only want to consider the case where S1-S2=00, you can do it easily by using a
different set_active_clocks command:
pt_shell> set_clock_groups -logically_exclusive -name mux1 \
          -group {CK1} -group {CK2}
pt_shell> set_clock_groups -logically_exclusive -name mux2 \
          -group {CK3} -group {CK4}
pt_shell> set_active_clocks {CK1,CK3}



 

Design Compiler再了解(五十四)

Using Multiple Clocks

有三種可能的多重clocks
1. Synchronous,
2. Asynchronous,
3. Exclusive Clocks

比較特別的是set_clock_groups的使用

If you specify more than two groups, each group is exclusive with respect to the other
specified groups. For example,
pt_shell> set_clock_groups -logically_exclusive \
          -group {CK1 CK2} -group {CK3 CK4} -group {CK5}

If you specify just one group, that group is exclusive with respect to all other clocks in the
design. For example,
pt_shell> set_clock_groups -logically_exclusive  -group {CK1 CK2}


You can optionally assign a name to a clock group declaration, which makes it easier to later
remove that particular declaration:
pt_shell> set_clock_groups -logically_exclusive -name EX1 \
          -group {CK1 CK2} -group {CK3 CK4}
Use the remove_clock_groups command to remove a clock grouping declaration:
pt_shell> remove_clock_groups -logically_exclusive -name EX1


To remove all exclusive clock grouping declarations made with the set_clock_groups
command:
pt_shell> remove_clock_groups -logically_exclusive -all

2011年9月22日 星期四

PrimeTime再了解(二十二)

一個範例關於多個clocks的設定方法
這些方法是從PrimeTime的文件抽出
但一樣適用於Desing Compile
 
Four Clocks and One Selection Signal
有不同的寫法



設定方法1
One way to prevent checking between unrelated clocks is to set a false path between the
clocks. For example,
pt_shell> set_false_path -from CK1 -to CK2
pt_shell> set_false_path -from CK2 -to CK1
pt_shell> set_false_path -from CK3 -to CK4
pt_shell> set_false_path -from CK4 -to CK3
pt_shell> set_false_path -from CK1 -to CK4
pt_shell> set_false_path -from CK4 -to CK1
pt_shell> set_false_path -from CK2 -to CK3
pt_shell> set_false_path -from CK3 -to CK2

In that case, PrimeTime tests all of the valid combinations of enabled clocks in a single run, while ignoring the invalid combinations. 


 

設定方法2
Another way is to use case analysis and set a logic value, either 0 or 1, on the SEL input, which checks the timing for a particular case of SEL=0 or SEL=1. 
For example,
pt_shell> set_case_analysis 0 [get_ports SEL]
With SEL=0, only CK1 and CK3 are active; CK2 and CK4 are ignored. If you want to analyze both cases, two analysis runs are necessary: one with SEL=0 and another with SEL=1. 

設定方法3 這個方法較適用於PT
Another method to accomplish the same effect is to use the set_disable_timing
command. For example, to disable checking of all paths leading from the CKP2 and CKP4 clock input pins of the design:
pt_shell> set_disable_timing [get_ports {CKP2 CKP4}]


設定方法4
Still another way is to specify which clocks can be active together at the same time and which clocks are currently active. For example,
pt_shell> set_clock_groups -logically_exclusive -name E1 \
            -group {CK1 CK3} -group {CK2 CK4}
pt_shell> set_active_clocks [all_clocks]

The set_clock_groups command defines groups of clocks that are exclusive with respect to each other. PrimeTime does not check paths that start from a clock in one group and end at a clock in another group. If you specify just one group, that group is considered exclusive with respect to all other clocks in the design.  


設定方法5
In the preceding example, the set_active_clocks command makes all four clocks active, so that PrimeTime analyzes all valid paths while avoiding the invalid clock combinations.
If you want to consider only the case where SEL=0, you can do it easily by using a different set_active_clocks command:
pt_shell> set_clock_groups -logically_exclusive -name E1 \
           -group {CK1 CK3} -group {CK2 CK4}
pt_shell> set_active_clocks {CK1,CK3}

Setting clocks CK1 and CK3 active means that CK2 and CK4 are inactive, which is just like using case analysis and setting SEL=0 or setting false paths between all combinations of clocks not using CK1 and CK3. 


Design Compiler再了解(五十三)

采用多重的时序异常命令

一个特殊的时序异常命令用于一个单独的时序路径,而一个一般的时序异常命令用于更多的时序路径。如果你对更多的实例执行给定的时序异常命令,那么更多的特殊命令将覆盖更多的一般的命令。
    下列规则定义了给定时序异常命令的优先顺序:
当你定义从一个管脚到另一个管脚的时序异常时,享有最高优先权
一个使用-from选项的命令比一个使用-to选项的命令享有更高的优先权
对于时序异常命令中的时钟,如果同时指定了-from-to选项, 它们将覆盖只指定了-from-to选项的共有同样路径的命令
    这个列表详细列出了由这些优先权规则定义的优先顺序:
1. command -from pin -to pin
2. command -from clock -to pin
3. command -from pin -to clock
4. command -from pin
5. command -to pin
6. command -from clock -to clock
7. command -from clock
8. command -to clock
    比如,在下列命令序列中,从AB的路径被看作是两循环路径,因为特殊命令覆盖了一般命令:
dc_shell> set_multicycle_path 2 -from A -to B
dc_shell> set_multicycle_path 3 -from A
    下列规则总结了时序异常命令的相互作用:
一般的set_false_path覆盖特殊的set_multicycle_path命令
一般的set_max_delay覆盖特殊的set_multicycle_path命令
特殊的set_false_path覆盖特殊的set_max_delay或set_min_delay 命令
特殊的set_max_delay命令覆盖特殊的set_multicycle_path命令

2011年9月21日 星期三

PrimeTime再了解(二十一)

link 與  link_design

在PT中才有link_design

link   The  link command, a synonym for the link_design command, exists
              in PrimeTime for compatibility with Design Compiler.

同樣為了通用性的script
建議用link

Design Compiler再了解(五十二)

为达到最小面积的最优化

資料由http://www.61ic.com/code/ 得來

4. resource sharing


强迫Design Compiler根据面积约束来执行资源分配和实现,在编译前设置下列变量:
dc_shell> set_resource_allocation area_only
dc_shell> set_resource_implementation area_only

    对一个明确的设计指定面积驱动的资源分配和实现,在编译前设置下列变量:
dc_shell> current_design subdesign
dc_shell> set_resource_allocation area_only
dc_shell> set_resource_implementation area_only


5.  flatten

绝大多数情况下,展开增加了面积。对于有不可预知的结构的非常随意的设计,展开可能减少面积。对那些可能从这种方法获益的特殊的模块使用set_flatten命令;不要对顶层设计使用set_flatten命令。-minimize-phase选项也能够减少面积。




6.跨层次边界的最优化

    Design Compiler总是注重层次级别和端口的功能。边界最优化,如穿越一个子设计的常数传播,不会自动发生。
    为能够细调面积,你可以保持层次,进行边界最优化。为更大程度地减少面积,你可能要移走层次间的边界。
1) 边界最优化(Boundary Optimization
利用下列的命令之一来指挥Design Compiler执行跨层次边界的最优化:
dc_shell> compile -boundary_optimization
dc_shell> set_boundary_optimization subdesign
    执行边界最优化,Design Compiler将传播常数、未连接的管脚和补足信息。一个设计里,有很多常数(VCC and GND)与子设计的输入相连,传播能够减少面积。



2) 移走层次(Hierarchy Removal
通过取消组来移走层次使得Design Compiler有更大的自由来共享跨越整个
设计的款项。取消设计工具部件的组也能够减少面积。

2011年9月20日 星期二

PrimeTime再了解(二十)

 link_path  與  link_library的差異


在PT中才有link_path
而link_library在DC及PT中都有


在PT中使用man去查 
  link_path
           Specifies  a  list of libraries, design files, and library files
              used during linking.


  link_library
              This is a synonym for the link_path variable.


而在DC中使用man去查 
   link_library
              Specifies  the  list  of  design files and libraries used during
              linking.


所以link_library == link_path
但是為了Script的共用性
建議採用link_library




Design Compiler再了解(五十一)

为达到最小面积的最优化

資料由http://www.61ic.com/code/ 得來

1.取消总的负延迟的最优化 Disable total negative slack optimization
    默认时,Design Compiler确定总的负延迟的优先级比面积约束高。这就意味着Design Compiler只对那些正延迟的路径进行面积最优化。
    在设置面积约束时,用-ignore_tns选项来改变默认的优先级:
dc_shell> set_max_area -ignore_tns max_area


2.允许时序面积恢复Enable sequential area recovery
    默认时,Design Compiler在最优化时并不重新映射时序元件。你可以通过重新映射那些不在临界路径上的时序元件来减少面积。为能够使用这个性能,设置compile_sequential_area_recovery变量为真。必须在编译前设置该变量:
dc_shell> compile_sequential_area_recovery = true

3.允许布尔最优化Enable Boolean optimization
    布尔最优化所用算法是以布尔代数的基本准则为基础。布尔最优化能够使用dont care条件将面积减到最小。这个算法只执行面积最优化;对于时序关键的设计不使用布尔最优化。
    使用compile_new_boolean_structure变量和set_structure命令的-boolean true选项使布尔最优化生效。必须在编译前运行这些命令:
dc_shell> compile_new_boolean_structure = true
dc_shell> set_structure true -boolean true -boolean_effort medium

2011年9月19日 星期一

Design Compiler再了解(五十)

最佳性能的最优化

資料由http://www.61ic.com/code/ 得來

方法四 执行高效果的、递增编译


一个递增的编译(-incremental_mapping编译选项)允许你实验不同的方法来递增地改进设计。递增的编译只适用于门级最优化,不适用于逻辑级最优化。设计性能的结果与原先设计的相同或更好。
为减少运行时间,你可以对那些已经达到时序要求的所有模块设置dont_touch属性:

dc_shell> dont_touch noncritical_blocks

dc_shell> compile -map_effort high -incremental_mapping

PrimeTime再了解(十九)

Timing closure efficiently

Grouping all of timing violations into several types:










set  ports_clock_root  [get_pins [all_fanout –flat –clock_tree –level 0]]
group_path  –name “Reg2Out”   –to [all_outputs]
group_path  –name “In2Reg”  \
–from [remove_from_collection [all_inputs] $ports_clock_root ]
group_path  –name  “Feedthrough”  \
-from [remove_from_collection [all_inputs] $ports_clock_root ]  \
-to [all_outputs]

把上面的這段script放在PT/DC中的report_timing之前

 Checking all violations
 report_constraint  -nosplit  -all_violators

report的順序如下























本區可參考網頁

http://kirenenko-tw.blogspot.com/2011/08/design-compiler_09.html

http://kirenenko-tw.blogspot.com/2011/08/design-compiler_5306.html

2011年9月18日 星期日

Design Compiler再了解(四十九)

最佳性能的最优化

資料由http://www.61ic.com/code/ 得來

方法三 展开关键路径的逻辑

由於不可能展开整个设计。在这里,你通过展开临界上的逻辑来提高性能。
    为展开临界路径上的逻辑,
1)用all_fanin命令来确定与临界路径相关的逻辑
dc_shell> all_fanin -to all_critical_pins() -only_cells
2)组合临界路径逻辑
dc_shell> group -design critical_block -cell_name cp1
3)描述临界路径逻辑的特色
dc_shell> characterize cp1
4)展开临界路径逻辑
dc_shell> current_design critical_block
dc_shell> set_flatten true
dc_shell> compile
dc_shell> set_flatten false
5)取消临界路径逻辑模块的组
dc_shell> current_design ..
dc_shell> ungroup -simple_names cp1

這樣只對需要優化的部份來展開
方便後續的其他動作

PrimeTime再了解(十八)

Specify false paths

設定false path的技巧
1.     Using Permutation and Combination [Mathematics] to set false paths
between all clock domains
2.     To hide the false paths which are relationship with each clock domain

以下是一個簡單例
## False paths from CLKC domain to the other domain
set_false_path –from [get_clock “CLKC” ]  -to [get_clock “CLKD”]
set_false_path –from [get_clock “CLKD” ]  -to [get_clock “CLKC”]
set_false_path –from [get_clock “CLKC” ]  -to [get_clock “gc_CLKD_1”]
set_false_path –from [get_clock “gc_CLKD_1” ]  -to [get_clock “CLKC”]
set_false_path –from [get_clock “CLKC” ]  -to [get_clock “gc_CLKD_2”]
set_false_path –from [get_clock “gc_CLKD_2” ]  -to [get_clock “CLKC”]

## False paths from CLKD domain to the other domain
## 紅色部分為可不設的重覆部份,因為前面已經會設定下面的部份
## set_false_path –from [get_clock “CLKD” ]  -to [get_clock “gc_CLKD_1”]
## set_false_path –from [get_clock “gc_CLKD_1” ]  -to [get_clock “CLKD”]
## set_false_path –from [get_clock “CLKD” ]  -to [get_clock “gc_CLKD_2”]
## set_false_path –from [get_clock “gc_CLKD_2” ]  -to [get_clock “CLKD”]

## False paths from gc_CLKD_1 domain to the other domain
set_false_path –from [get_clock “gc_CLKD_1” ]  -to [get_clock “gc_CLKD_2”]
set_false_path –from [get_clock “gc_CLKD_2” ]  -to [get_clock “gc_CLKD_1”]

另外
Setting false paths for test_mode/scan_enable signals

本區其他參考頁
http://kirenenko-tw.blogspot.com/2011/08/design-compiler_5306.html

http://kirenenko-tw.blogspot.com/2011/08/design-compiler_14.html