DFT再了解(九)

How many test signals does DFT need?

























test_clock :
The normal function clock(s) would be used as test_clock(s).
Test clock should be planned for ATPG operation.
Minimize usage of internally-derived clock signals.
Avoid using bi-directional ports as test_clock.

test_reset :
Make DUT easy to reset No complex initialization.
Prefer a plain asynchronous reset at primary input port.


scan_test & scan_enable :
Avoid using shared pin(s) for scan_mode and scan_enable.
If shared pin(s) is used for scan_enable or scan_mode, The function
patterns with conflict of mode switching, the fault coverage will
degrade.
It is best to have two extra input pins(dedicated pins). One is for
scan_mode and the other is for scan_enable.
Avoid using bi-directional ports as scan_mode and scan_enable.

scan_in & scan_out :
To minimize package pins ,the scan input/output pins can be shared
with the function input/output pins pads.