DFT再了解(十)

DFT Integration Architecture

The DFT integration architecture should follow the suggestions below:
To accommodate the different test requirements, mode generator and multiple test architecture must be provided on the same test design.

In order to observe the boundary signals of a specific building block in normal
mode or test output signals in different test modes , the plan must be provided to
enable debugging function flexibility

When the I/O pin count is a limited design resource, the test pins used in DFT implementation should be shared with the chip function pins.

The shared pins will be applied to DFT control signals or data input/output signals.

The shared pins could be input、output or bi-directional pins

If the shared pins as bi-directional pins should be controlled to place in the input
status or output status.

The test clock and test reset signals should be easily controllable.













There are four main blocks added in the integration architecture, Mode Generation
Module, Debug Module, Clock Manage Module and Reset Manage Module.

Mode Generation Module and Debug Module:
The function of Mode Generation Module is mainly used to generate test
enable signals and dealt with pin sharing while the function of Debug module is
used to multiplex function block outputs and DFT object outputs.

Clock Manage Module:
The function of Clock_mng Module is integrated all of external clock and
internal clock signals and used to multiplex normal clocks and test clocks.

Reset Manage Module:
The function of Reset_mng Module is integrated all of software Set/Reset and
hardware Set/Reset signals and used to multiplex normal set/resets and test
resets.

To ease integration to arrange the Mode Generation Module in level 1,and the
Debug Module、Clock Manage Module and Reset Manage Module in level 2 of
the design hierarchy.