Design Compiler再了解(三十六)

Multiple Input/Output Paths

先看input的部份












create_clock -period 2 [get_ports Clk]
set_input_delay -max 0.3 –clock Clk –clock_fall [get_ports A]
set_input_delay -max 1.2 –clock Clk –add_delay [get_ports A]



再看output的部份
multi-output delay的設法也是一樣的
set_output_delay –max 2.5 –clock Clk [get_ports B]
set_output_delay –max 0.7 –clock Clk - clock_fall –add_delay \
[get_ports B]