DFT再了解(二)

Full Scan Summary

Full Scan Advantages:
Needs only combinational ATPG (D-algorithm)
for testing all Stuck-At faults

Combinational ATPG gives shorter ATPG run times

Predictable and applies across most architectures

Gives highest test coverage of all the algorithms

Easiest to implement



Full Scan Limitations:
Adds nonfunctional pins to the package

Timing and density impact of scan-equivalent flops

Embedded memory, latches, and non-scan flip-flops,
require fast sequential ATPG (“almost-full scan”)