
1. Highly pushbutton—little intervention by designer
2. Each design is checked against a set of DRC rules
3. Violations are corrected by adding or modifying logic
The complexity of SoC designs is driving the need for structured DFT methodologies. A
structured methodology is one that globally resolves many on-chip testability issues. Such
methodologies are widely applicable to most designs without much customization. They are
automated. The tools do most of the DFT work with minimal intervention. Scan-based testing is
a typical structured methodology that will be emphasized in this course. Scan insertion, for
example, is relatively automated and independent of design function.
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