不良RTL設計的探討

一個不良的設計






1. Design Compiler must preserve block pin definitions
Logic optimization – e.g. merging of combinational logic -
does not occur across block boundaries

2. Path from REG A to REG C may be larger and slower
than necessary Poorly partitioned!

不良的設計會導致合成上問題，應該盡可能的避免。
當然coding style也會產生其它的問題，
此處可查閱相關的RTL coding style
synopsys的內部文件有相關的說明


較好的設計








1. Related combinational logic is grouped into one block:
No hierarchy separates combinational functions
A, B, and C

2. Combinational optimization techniques can now be
fully exploited Faster and smaller combo logic!

3. However, no sequential optimization possible at REG C



另一種較差的設計













在Design的TOP總是會有一些Glue Logic來連結次module
但是如果全部都是自己作的就可以將上面的NAND放到C module下
而如果是整合的人，因為設計不是你，所以不得已還是會用到Glue Logic

Synopsys有提供一些注意事項
1. No combinational optimization between glue logic and combo logic C

2. If the top-level blocks A, B and C are large and will be synthesized
separately (middle-up compile strategy), an additional compile is
needed at top-level


最後
(Quality of Results – QoR) relies on good coding style
(Quality of Source – QOS).