Design Compiler再了解(十五)

check_design

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
link
check_design ##
source TOP.con ...

The check_design command, just like the link command, returns a ‘1’ or ‘0’ value to indicate if the
action was completed without, or with any serious problems, respectively.

可以把上面script改成如下

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
if {[link] ==0} {
echo “Linking Error”
exit; # Exits DC if a serious linking problem is encountered
}
if {[check_design] ==0} {
echo “Check Design Error”
exit; # Exits DC if a check-design error is encountered
} ; # Script continues to execute if NO problems encountered
source TOP.con
compile –boundary –scan –map high