Design Compiler再了解(八)

特別注意事項

Do not set an external input delay on the clock port !

dc_shell-t> create_clock -period 10 [get_ports CLK]
dc_shell-t> set_input_delay 3 -clock CLK \
[remove_from _collection [all_inputs] [get_ports CLK]]




Do not forget the clock controlling a port external delay!  If needed create a virtual clock.

dc_shell-t> create_clock -p eriod 10 -name VIRT_CLK
dc_shell-t> set_input_delay 3 -clock VIRT_CLK [get_ports A]


Do not use max/min delays to constraint combo logic!

dc_shell-t> create_clock -period 12 -name CLK_VIRT
dc_shell-t> set_input_delay 0 -clock CLK_VIRT [get_ports A]
dc_shell-t> set_output_delay 0 -clock CLK_VIRT [get_ports B]


Do not forget to fully specify the constraints!
By default (without -fall/-rise or -max/-min), commands are symmetric 

dc_shell-t> set_input_delay -fall 3 -clock CLK [get_ports A]
dc_shell-t> set_input_delay -rise 2 -clock CLK [get_ports A]