Design Compiler再了解(十七)

Saving the ddc Design After compile給ICC使用

read_verilog {A.v B.v TOP.v}
current_design MY_TOP
link
check_design
write –format ddc –hier –output unmapped/MY_TOP.ddc
source TOP.con
check_timing
compile –boundary –scan –map high
change_names –rule verilog -hier
write –format verilog –hier –output mapped/MY_TOP_ntl.v 1
write –format ddc –hier –output mapped/MY_TOP.ddc

The ddc format stores the design netlist, constraints and
attributes. This is an efficient format to either re-read the
design into DC or to read the design into ICC.