Design Compiler再了解(十八)

Reading Designs with analyze & elaborate

set search_path “$search_path rtl unmppd mppd”
analyze –format verilog {A.v TOP.v}
Compiling source file .../risc_design/rtl/A.v
Compiling source file .../risc_design/rtl/TOP.v
elaborate MY_TOP
...
Current design is now ‘MY_TOP’
Reading ddc file ‘.../risc_design/unmppd/MY_B.ddc’.
Reading ddc file ‘.../risc_design/mppd/MY_C.ddc’.

取代了 current_design or link!

analyze
- Reads source code files (Verilog or VHDL RTL)
- Checks syntax and issues errors/warnings
- Converts both Verilog and VHDL files into intermediate binary format files, placed in CWD
- Can use define_design_libto redirect the files/directories to a sub-directory


elaborate
- Reads the intermediate .pvl files and builds the ‘GTECH’ design in DC memory (unmapped
ddc format)
- Sets the current design to the specified design
- Links and auto-loads the specified design
- Allows specification of parameter values: elaborate MY_TOP -parameters “N=8, M=3”.
- Caution: If available, a .ddc file will be loaded and will over-write an RTL source code
design that was explicitly analyzed, if the .ddc file is found in the search_path directories.

當TOP如下時
module MY_TOP (A, B, C, ... );
parameter A_WIDTH 2;
parameter B_WIDTH 4; ...
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B; ...
MY_A U1 (.A1 (A), ...
MY_B U2 (.B1 (B), ...

elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16”
可以在此設定變數值

elaborate是設定變數值的唯一的方法