update_timing
Updates timing for the current design and prepares the design for further analysis
Some commands such as report_timing or report_constraint
automatically call update_timing if needed
report_bottleneck (PT only)
Reports the common point in the design that contributes to
multiple violations
report_constraint (DC可用)
By default will return the synthesis cost function with all costs, weights and weighted costs
Can report all violators for max/min timing and DRC verbose switch is not recommended
-verbose switch is not recommended
report_timing
By default shows the worst max path per path group
report_timing -exceptions all (DC可用)
report_delay_calculation 2006.06 feature – The exceptions option names exceptions (mutli-cycle paths, and
min/max delays) that are related to the reported timing path
Shows the delay calculation for a pin-to-pin timing arc
Library needs to be enabled for delay calculation reports
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