ATPG再了解(十一)

Memory DFT Strategies

A. Testing RAM/ROM for Internal Faults:
The transistor-level fabric of a RAM/ROM can’t be tested by gate-level
stuck-at-fault techniques. Use direct pin access or memory BIST.


B. Applying a Black-Box Model:
A vendor RAM/ROM primitive in a synthesized design often behaves
as a black box. This casts a low-coverage shadow over nearby logic.


C. Inserting Test Points:
The testability of shadow logic can be improved by automatic insertion
of DFT control-and-observe test points around a black-box RAM/ROM.


D. Writing Functional Models:
Testability of shadow logic can be maximized by replacing the black box
RAM/ROM cell with a user-supplied functional Verilog model.