Design Compiler再了解(四十五)

set_disable_timing 與 set_false_path 的差別


set_disable_timing: Applications of this command include disabling
timing arc of a cell in order to break the combinational feedback loop(in DC-SYN),
or to instruct PT to exclude a particular timing arc (thus the path segment) from
analysis(in PT-STA).

set_disable_timing –from
–to


可以看下圖
在reset上面delay特大，為了不要影響整個合成
我們只針對reset這個PATH(A->Z)設set_disable_timing












set_false_path command will remove all timing constraints from the path. Tools still calculate the path delay, but don't report it to be an error. While set_disable_timing will remove paths from timing analysis. So you can see set_disable_timing is more efficient than set_false_path command.

這些constraints 必須延用到STA，否則會有timing上的錯誤