DFT 名詞解釋

SA1 Fault:
Due to a defect, input pin A
of U0acts as if stuck high,
independent of input signal

SA0 Fault:
Due to defect, output pin Y
of U1acts as if stuck low,
independent of the inputs

Fault Model:
A logical model representing the effects of a physical defect

Stuck-At Fault (SAF)

Single Stuck-At Fault (SSAF)

defective parts per million (DPPM)

The testable flip-flop has two modes:
Normal mode—where the ASIC is operating as it was functionally designed to operate.
Test mode—where the ASIC is undergoing manufacturing test.

Level-sensitive scan design (LSSD) is a latch-based replacement for single latches,
master-slave latches, or flip-flops. It requires three separate clock lines to be routed.

A Full Scan design is one in which all of the flip-flops in the design have been scan replaced and will be included in the scan-chain.
Note: No memories, latches.

there are three additional ports now: SI (Scan In), SO (Scan Out), and SE (Scan Enable).
The command to stitch up the scan-chains is: insert_dft.