DelayLine的設計

想不出要寫甚麼，把很久以前的東東貼出來分享

一個很簡單的delay line的電路設計

// DLY4X1 : 0.536;0.728;1.238
// DLY3X1 : 0.394;0.536;0.916
// DLY1X1 : 1.167;0.225;0.382

module dly_line(line_in,
dly_sel,
src_sel,
line_out);

input line_in;
input [1:0] dly_sel;
input [1:0] src_sel;
output line_out;

wire line_in;
//wire dly_0;
wire dly_1;
wire dly_2;
wire dly_3;
wire dly_4;

wire out_4;
reg out_3;
wire out_2;
wire out_1;

reg line_out;

//DLY2X1 u_dly_0 (.A(line_in), .Y(dly_0));
//DLY4X1 u_dly_1 (.A(dly_0), .Y(dly_1));
DLY4X1 u_dly_1 (.A(line_in), .Y(dly_1));
DLY4X1 u_dly_2 (.A(dly_1), .Y(dly_2));
DLY4X1 u_dly_3 (.A(dly_2), .Y(dly_3));
DLY4X1 u_dly_4 (.A(dly_3), .Y(dly_4));

assign out_4 = ~out_3;
assign out_1 = line_in;
assign out_2 = ~line_in;



always @(dly_sel or dly_1 or dly_2 or dly_3 or dly_4 or out_4)
case(dly_sel)
2'b00 : out_3 = dly_1;
2'b01 : out_3 = dly_2;
2'b10 : out_3 = dly_3;
2'b11 : out_3 = dly_4;
endcase

always @(src_sel or out_1 or out_2 or out_3 or out_4 or line_out)
case(src_sel)
2'b00 : line_out = out_1;
2'b01 : line_out = out_2;
2'b10 : line_out = out_3;
2'b11 : line_out = out_4;
endcase

endmodule