UVM Sequence再了解(七)

關於Sequence Action Macro
一般我們會用的大概就是
`uvm_do或是`uvm_do_with

其它的使用機會就少的多了



List Of Sequence Action Macros:

整理自http://testbench.in/UT_08_UVM_SEQUENCE_2.html


These macros are used to start sequences and sequence items that were either registered with a <`uvm-sequence_utils> macro or whose associated sequencer was already set using the method.

`uvm_create(item/sequence)

This action creates the item or sequence using the factory. Only the create phase will be executed.

`uvm_do(item/sequence)

This macro takes as an argument a uvm_sequence_item variable or sequence . All the above defined 7 phases will be executed.

`uvm_do_with(item/sequence, Constraint block)

This is the same as `uvm_do except that the constraint block in the 2nd argument is applied to the item or sequence in a randomize with statement before execution.

`uvm_send(item/sequence)

Create phase and randomize phases are skipped, rest all the phases will be executed. Using `uvm_create, create phase can be executed. Essentially, an `uvm_do without the create or randomization.

`uvm_rand_send(item/sequence)

Only create phase is skipped. rest of all the phases will be executed. User should use `uvm_create to create the sequence or item.

`uvm_rand_send_with(item/sequence , Constraint block)

Only create phase is skipped. rest of all the phases will be executed. User should use `uvm_create to create the sequence or item. Constraint block will be applied which randomization.

`uvm_do_pri(item/sequence, priority )

This is the same as `uvm_do except that the sequence item or sequence is executed with the priority specified in the argument.

`uvm_do_pri_with(item/sequence , constraint block , priority)

This is the same as `uvm_do_pri except that the given constraint block is applied to the item or sequence in a randomize with statement before execution.

`uvm_send_pri(item/sequence,priority)

This is the same as `uvm_send except that the sequence item or sequence is executed with the priority specified in the argument.

`uvm_rand_send_pri(item/sequence,priority)

This is the same as `uvm_rand_send except that the sequence item or sequence is executed with the priority specified in the argument.

`uvm_rand_send_pri_with(item/sequence,priority,constraint block)

This is the same as `uvm_rand_send_pri except that the given constraint block is applied to the item or sequence in a randomize with statement before execution.


Following macros are used on sequence or sequence items on a different sequencer.


`uvm_create_on(item/sequence,sequencer)

This is the same as `uvm_create except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified sequencer argument.

`uvm_do_on(item/sequence,sequencer)

This is the same as `uvm_do except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified sequencer argument.

`uvm_do_on_pri(item/sequence,sequencer, priority)

This is the same as `uvm_do_pri except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified sequencer argument.

`uvm_do_on_with(item/sequence,sequencer, constraint block)

This is the same as `uvm_do_with except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified sequencer argument. The user must supply brackets around the constraints.

`uvm_do_on_pri_with(item/sequence,sequencer,priority,constraint block)

This is the same as `uvm_do_pri_with except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified sequencer argument.


Examples With Sequence Action Macros:


virtual task body();
uvm_report_info(get_full_name(),
"Executing Sequence Action Macro uvm_do",UVM_LOW);
`uvm_do(req)
endtask

virtual task body();
uvm_report_info(get_full_name(),
"Executing Sequence Action Macro uvm_do_with ",UVM_LOW);
`uvm_do_with(req,{ inst == ADD; })
endtask

virtual task body();
uvm_report_info(get_full_name(),
"Executing Sequence Action Macro uvm_create and uvm_send",UVM_LOW);
`uvm_create(req)
req.inst = instruction::PUSH_B;
`uvm_send(req)
endtask

virtual task body();
uvm_report_info(get_full_name(),
"Executing Sequence Action Macro uvm_create and uvm_rand_send",UVM_LOW);
`uvm_create(req)
`uvm_rand_send(req)
endtask