What happens If the C gate net has a longer than expected delay?
PT automatically performs gating checks if clock gating logic exists
Setup and hold constraints are set to zero
Apply specific setup and hold constraints using “set_clock_gating_check”
請參考下面的constraint
create_clock -period 10 [get_ports CLK]
set_clock_gating_check -setup 0.5 -hold 0.4 [get_clocks CLK]
