2011年7月17日 星期日

Design Compiler再了解(六)

Uncertainty

Uncertainty models the maximum delay difference between
the clock network branches, known as clock skew,
but can
also include clock jitter and margin effects:







The default clock uncertainty is zero.
Uncertainty can also be defined between clock domains with as follows:
set_clock_uncertainty –setup TU –from clk1–to clk2
















By default, the command “set_clock_uncertainty” assigns the same value to the setup
and the hold uncertainty, unless either the –setup or the –hold switch are used.

This allows the design to be synthesized with extra “clock period margin” for setup timing, which does not apply to hold timing.