$value$plusargs 的測試例

這是從systemverilog ＩＥＥＥ1800-2009挖出的測試例

// IUS
使用irun test.sv +TEST=5 +TESTNAME=test001 +TESTG1=test01 +FREQ+=9.33

//VCS
vcs test.sv
simv +TEST=5 +TESTNAME=test001 +TESTG01=tes01 +FREQ=9.33


`define STRING logic [1024 * 8:1]

module goodtasks;
`STRING str;
integer i1;
logic [31:0] vect;
real realvar;

real frequency;
logic [8*32:1] testname;
logic [64*8:1] pstring;
logic clk;

// vcs2009 logic 不支援，要改成reg才能用

initial begin
if ($value$plusargs("TEST=%d", i1))
$display("value was %d", i1);
else
$display("+TEST= not found");

if ($value$plusargs("TESTNAME=%s",testname)) begin
$display(" TESTNAME= %s.",testname);
$finish;
end


pstring = "TESTG%d";

　　// 此處ＩＵＳ92及vcs2009.12未支援
if ($value$plusargs(pstring, testname))
$display("Running test number %0d.",testname);

　　// 此處ＩＵＳ92及vcs2009.12未支援
if (!($value$plusargs("FREQ+%0F",frequency)))
frequency = 8.33333; // 166 MHz

$display("frequency = %f",frequency);


#100 $finish;
end

endmodule

支援的變數列表如下
%d decimal conversion
%o octal conversion
%h, %x hexadecimal conversion
%b binary conversion
%e real exponential conversion
%f real decimal conversion
%g real decimal or exponential conversion
%s string (no conversion)