ATPG再了解(十五)

Verilog DPV Testbench Overview

The Verilog direct pattern validation (Verilog DPV) testbench is a tool that lets you directly
simulate and validate STIL test patterns generated by TetraMAX and Boundary-scan test
vectors generated by BSD Compiler.

The tool eliminates the need to generate intermediate formats or additional simulator
constructs.

Verilog DPV testbench consists of a set of PLI tasks that function with the Verilog simulator.

In TetraMAX, issue a write_patterns <pfile.ext> -format [stil | stil99]
command to generate the Verilog testbench. For example:

test> write_patterns pfile.stil -format stil99

The name of the generated testbench file, in this case, would be pfile_stildpv.v, where
TetraMAX replaces the file extension (here, “.stil”), with “_stildpv.v”. Verilog DPV.

TetraMAX generates a Verilog-formatted testbench that contains an instance of the device
to be tested and includes appropriate connections to the Verilog DPV testbench interface.
The testbench contains the necessary calls to the Verilog DPV testbench PLI tasks.

When you run the Verilog simulation, Verilog DPV testbench applies STIL-formatted test
data as stimulus to the design and validates the design’s response against the
STIL-specified expected data. The simulation results ensure both the logical operation and
timing sensitivity of the final STIL test patterns generated by TetraMAX.

Verilog DPV testbench validates the simulated device response against the timed output
response defined by STIL. For windowed data, it confirms that the output response is stable
within the windowed time region.

Note:
1.  To use Verilog DPV, you must have access to GCC (GNU Compiler Collection) 3.2.2 and
ld: Software Generation Utilities - 5.9-1.388.
2. Verilog DPV might not work on unsupported operating platforms or simulators. See the
release notes for a list of supported platforms and simulators.

3. The validation of DPV testbench for IDDQ STIL patterns is not supported.

Then, to simplify the procedures, point the environment variable STILDPV_HOME to the
stildpv directory where you installed Verilog DPV testbench. For example, in a typical
Synopsys installation using csh, the command is:
setenv STILDPV_HOME $SYNOPSYS/<platform>/stildpv

where $SYNOPSYS is the Synopsys software installation directory.
The operations in the following sections use the STILDPV_HOME environment variable to
designate the location of Verilog DPV testbench code. 

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