build_phase的使用

當我們一開始UVC時，須先設定UVC內部的變數與環境。
我們會使用build_phase這個function來作

在Agent中
我們會建立monitor, sequencer, driver
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase)
monitor = simple_monitor::type_id::create("monitor",this);
if (is_active == UVM_ACTIVE) begin
// Build the sequencer and driver.
sequencer =
uvm_sequencer#(simple_item)::type_id::create("sequencer",this);
driver = simple_driver::type_id::create("driver",this);
end
endfunction : build_phase

個別的class如drvier內部也會有build_phase
去設定所需的變數，此例使用uvm_config_db
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual ubus_if)::get(this, "", "vif", vif))
`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"});
endfunction: build_phase

在更上層的env中，我們可以用此來設定環境變數，
如Master/Slave數目
virtual function void build_phase(phase);
string inst_name;
super.build_phase(phase);
if(!uvm_config_db#(virtual ubus_if)::get(this,””,
"vif",vif))
`uvm_fatal("NOVIF",{"virtual interface must be set for: ",
get_full_name(),".vif"});
masters = new[num_masters];
for(int i = 0; i < num_masters; i++) begin
$sformat(inst_name, "masters[%0d]", i);
masters[i] = ahb_master_agent::type_id::create(inst_name,this);
end
// Build slaves and other components.
endfunction

所有的build_phase，一定不能忘記super.build_phase(phase);
Properties that are registered as UVM fields using the uvm_field_* macros will be automatically updated by the component’s super.build_phase() method. These properties can then be used to determine the build_phase() execution for the component.