模拟 (SIMULATORS)
A. 在实现前模拟，可以及时的发现错误，改正错误
B. 模拟是现实近似。为了降低难度，模拟中很多特征都
简化了，甚至被忽略。(Analog較常發生)
C. 模拟实际能实现的是对设计的说明进行，而且还必须
以严格的语法来说明。
D. 不能确定模拟和实际的差别。不能证明模拟完全无
错，其功能的正确性和模型的精确性始终值得怀疑。
1 激励与响应 (Simulation requires stimulus)
• 模拟要求提供一个测试平台
• 目标是如何建立测试平台。
• 测试平台提供设计所需的输入，模拟器依据设计会作出响应。
• 设计者本人根据模拟器的输出结果来判断设计的正确性。
• 在一定条件下给了模拟器一个激发信号后，检查其输出，判断
其响应是否符合要求。
2 事件驱动模拟 (Event-Driven Simulation )
—Simulators are never fast enough.
—Outputs change only when an input changes.
只有输入变化时才进行模拟。因此模拟程序是由输
入的变化驱动的，称事件驱动。
• 输入变化，即使输出不变化，也进行模拟
• 满足事件触发条件
3 基于时钟周期的模拟 (Cycle-Based Simulation)
— Cycle-based simulators collapse combinatorial logic into
equations.
• When the circuit description is compiled, all combinatorial
functions are collapsed into a single expression that can be used
to determine all flip-flop input values based on the current state of
the fan-in flip-flops.
• During simulation, whenever the clock input rises, the value of all
flip-flops is updated using the input value returned by the pre-
compiled combinatorial input functions.
—Cycle-based simulations have no timing information.
• This great improvement in simulation performance comes at a
cost: all timing and delay information is lost. 不考虑定时与延迟信息
• Cycle-based simulators assume that the entire design meets the
set-up and hold requirements of all the flip-flops. 设计满足触发器
建立和保时的时间要求
• When using a cycle-based simulator, timing is usually verified
using a static timing analyzer. 基于时钟周期的模拟，使用静态时序
分析器分析时序
— Cycle-based simulators can only handle synchronous
circuits. (仅能用于同步电路)
• Cycle-based simulators further assume that the active clock edge
is the only significant event in changing the state of the design. 有
效的时钟边沿触发状态改变
• All other inputs are assumed to be perfectly synchronous with the
active clock edge. 所有输入被有效的时钟边沿同步
• Therefore, cycle-based simulators can only simulate perfectly
synchronous designs. 仅能用于同步设计
• Anything containing asynchronous inputs, latches, or multiple-
clock domains cannot be simulated accurately.
4 共同模拟Co-Simulators
设计中的同步部份用的是时钟驱动，而其它部份用的是事件驱
动。两种模拟结合起来共同完成模拟功能。
Multiple simulators can handle separate portions of a design
—All simulators operate in locked-step.
• During co-simulation, all simulators involved progress along the time
axis in lock-step.
• All are at simulation time T1 at the same time and reach the next
time T2 at the same time.
• This implies that the speed of a co-simulation environment is limited
by the slowest simulator.
—Performance is decreased by the communication and
synchronization overhead.
—Translating values and events from one simulator to
another can create ambiguities.
Co-simulation should no be confused with single-kernel
simulation
